參數(shù)資料
型號： PXA250
廠商： Intel Corp.
英文描述： Intel-R PXA250 and PXA210 Applications Processors
中文描述： 英特爾- R的PXA250和PXA210應用處理器
文件頁數(shù)： 14/46頁
文件大?。?/td> 431K
代理商： PXA250
PXA250 and PXA210
—
Electrical, Mechanical, and Thermal Specification
14
Datasheet
Miscellaneous Pins
BOOT_SEL
[2:0]
IC
Boot programming select pins. These pins are sampled to indicate the type of
boot device present per the following table;
BOOT_SEL[2:0]
Description
000
Asynchronous 32-bit ROM
001
Asynchronous 16-bit ROM
010
Reserved
011
Reserved
100
One 32-bit SMROM
101
One 16 bit SMROM
110
Two 16 bit SMROMs (32 bit bus)
111
Reserved
PWR_EN
OCZ
Power Enable. Active high output.
PWR_EN enables the external power supply. Negating it signals the power supply
that the system is going into sleep mode and that the VDD power supply should
be removed.
nBATT_FAUL T
IC
Battery Fault. Active low input.
Signals the applications processor that the main power source is going away
(battery is low or is removed from the system.) The assertion of nBATT_FAULT
causes the applications processor to enter Sleep Mode. The device will not
recognize a wakeup event while this signal is asserted.
nVDD_FAULT
IC
VDD Fault. Active low input.
Signals the applications processor that the main power source is going out of
regulation (i.e. shorted card is inserted). nVDD_FAULT causes the device to enter
Sleep Mode. nVDD_FAULT is ignored after a wakeup event until the power supply
timer completes (approximately 10 ms).
nRESET
IC
Hard reset. Active low input.
nRESET is a level sensitive input which starts the processor from a known
address. A LOW level causes the current instruction to terminate abnormally, and
all on-chip states to be reset. When nRESET is driven HIGH, the processor re-
starts from address 0. nRESET must remain LOW until the power supply is stable
and the internal 3.6864 MHz oscillator has come up to speed. While nRESET is
LOW the processor performs idle cycles.
nRESET_OUT
OC
Reset Out. Active low output.
This signal is asserted when nRESET is asserted and deasserts after nRESET is
negated but before the first instruction fetch. nRESET_OUT is also asserted for
“
soft
”
reset events (sleep, watchdog reset, GPIO reset)
JTAG Pins
nTRST
IC
JTAG Test interface reset. If JTAG is used, then you must drive nTRST from low
to high either before or at the same time as nRESET
If JTAG is not used, then tie nTRST to either nRESET or low.
TDI
IC
JTAG test interface data input. Note this pin has an internal pullup resistor.
TDO
OCZ
JTAG test interface data output. Note this pin does NOT have an internal pullup
resistor.
TMS
IC
JTAG test interface mode select. Note this pin has an internal pullup resistor.
TCK
IC
JTAG test interface reference Clock. TCK is the reference clock for all transfers
on the JTAG test interface. Note this pin has an internal pulldown resistor.
TEST
IC
Test Mode. You must ground this pin. This pin is for manufacturing purposes only.
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 6 of 7)
Name
Type
Description
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