參數(shù)資料
型號(hào)： PXA250
廠商： Intel Corp.
英文描述： Intel-R PXA250 and PXA210 Applications Processors
中文描述： 英特爾- R的PXA250和PXA210應(yīng)用處理器
文件頁(yè)數(shù)： 10/46頁(yè)
文件大?。?/td> 431K
代理商： PXA250
PXA250 and PXA210
—
Electrical, Mechanical, and Thermal Specification
10
Datasheet
SDCLK[2:0]
OCZ
SDRAM and/or Synchronous Static Memory clocks. Connect SDCLK[0] to the
clock (CLK) pins of SMROM and SDRAM-timing Synchronous Flash. SDCLK[1]
and SDCLK[2] should be connected to the clock pins of SDRAM in bank pairs 0/1
and 2/3, respectively. They are driven by either the internal memory controller
clock, or the internal memory controller clock divided by 2. At reset, all clock pins
are free running at the divide by 2 clock speed and may be turned off via free
running control register bits in the memory controller. The memory controller also
provides control register bits for clock division and deassertion of each SDCLK
pin. SDCLK[0] control register assertion bit defaults to on if the boot-time static
memory bank 0 is configured for SMROM or SDRAM-timing Synchronous Flash.
SDCLK[2:1] control register assertion bits are always deasserted upon reset.
0 and 2 are not three-stateable, SDCLK1 is three-stateable
nCS[5]/
GPIO[33]
ICOCZ
Static chip selects. These signals are chip selects for static memory devices such
as ROM and Flash. They are individually programmable in the memory
configuration registers. nCS[5:3] may be used with variable data latency variable
latency I/O devices.
See Note [1]
nCS[4]/
GPIO[80]
ICOCZ
Static chip select 4.
nCS[3]/
GPIO[79]
ICOCZ
Static chip select 3.
nCS[2]/
GPIO[78]
ICOCZ
Static chip select 2.
nCS[1]/
GPIO[15]
ICOCZ
Static chip select 1.
nCS[0]
ICOCZ
Static chip select 0. This is the boot memory chip select. nCS[0] is a dedicated
pin.
RD/nWR
OCZ
Read/Write for static interface. Intended for use as a steering signal for buffering
logic
RDY/
GPIO[18]
ICOCZ
Variable Latency I/O Ready pin (input)
See Note [1]
PCMCIA/CF Control Pins
nPOE/
GPIO[48]
ICOCZ
PCMCIA Output Enable. This PCMCIA signal is an output and performs reads
from memory and attribute space.
See Note [1]
nPWE/
GPIO[49]
ICOCZ
PCMCIA Write Enable. This signal is an output and performs writes to memory
and attribute space.
See Note [1]
nPIOW/
GPIO[51]
ICOCZ
PCMCIA I/O Write. This signal is an output and performs write transactions to the
PCMCIA I/O space.
See Note [1]
nPIOR/
GPIO[50]
ICOCZ
PCMCIA I/O Read. This signal is an output and performs read transactions from
the PCMCIA I/O space.
See Note [1]
nPCE[2:1]/
GPIO[53, 52]
ICOCZ
PCMCIA Card Enable. These signals are outputs and select a PCMCIA card. Bit
one enables the high byte lane and bit zero enables the low byte lane.
See Note [1]
Table 2. Pin and Signal Descriptions for the PXA250 Applications Processor (Sheet 2 of 7)
Name
Type
Description
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