參數(shù)資料
型號(hào): PPC405EX-NpAfffTx
廠商: Applied Micro Circuits Corp.
英文描述: PowerPC 405EX Embedded Processor
中文描述: 嵌入式處理器的PowerPC 405EX
文件頁數(shù): 58/67頁
文件大小: 457K
代理商: PPC405EX-NPAFFFTX
PPC405EX – PowerPC 405EX Embedded Processor
58
AMCC Proprietary
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
DDR 1/2 SDRAM I/O Specifications
The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note:
MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
programming register. In a typical system, users advance MemClkOut by 90
°
. This depends on the specific
application and requires a thorough understanding of the memory system in general (refer to the DDR
SDRAM Controller chapter in the
PPC405EX Embedded Processor User’s Manual
).
The signals are terminated as indicated in
Figure 6
for the DDR timing data in the following sections.
Board Layout Restrictions
TBP
Clocking
TBP
Figure 6. DDR SDRAM Simulation Signal Termination Model
DDR2 SDRAM On-Die Termination Impedance Setting
For all DDR2 applications, the On-Die Termination (ODT) impedance value
must
be set to 75 ohms in the DIMM
Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.
10pF
10pF
MemClkOut
MemClkOut
120
Ω
50
Ω
30pF
Addr/Ctrl/Data/DQS/DM (DDR1)
V
TT
= SOV
DD
/2
PPC405EX
Addr/Ctrl (DDR2)
Note:
This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
It is
not
a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
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