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參數(shù)資料
| 型號： | PPC405EX-NpAfffTx |
| 廠商： | Applied Micro Circuits Corp. |
| 英文描述： | PowerPC 405EX Embedded Processor |
| 中文描述： | 嵌入式處理器的PowerPC 405EX |
| 文件頁數(shù)： | 40/67頁 |
| 文件大?。?/td> | 457K |
| 代理商： | PPC405EX-NPAFFFTX |
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PPC405EX – PowerPC 405EX Embedded Processor
40
AMCC Proprietary
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
System Interface
SysClk
System input clock.
I
3.3V tolerant
2.5V CMOS
receiver
1
SysErr
Machine check exception has occurred.
O
3.3V tolerant
2.5V CMOS
SysReset
Main system reset. This signal may be driven by the PPC405EX to
cause a board level reset to occur.
I/O
3.3V tolerant
2.5V CMOS
1, 2
TestEn
Test enable. Reserved for manufacturing LSSD test.
I
3.3V LVTTL
receiver
w/pull-down
3
Halt
External request to stop the processor.
I
3.3V LVTTL
receiver
w/pull-up
TmrClk
Processor timer external input.
I
3.3V LVTTL
receiver
w/pull-up
GPIO00:27
GPIO29:31
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends
on the setting of bits in the GPIO registers.
I/O
3.3V LVTTL
GPIO28
General purpose I/O. Most of the GPIO signals are multiplexed with
other signals. Which signal is connected to the external pin depends
on the setting of bits in the GPIO registers.
I/O
3.3V tolerant
2.5V CMOS
PSROUser
Performance screen ring output. Use for module characterization and
screening only.
O
3
Trace Interface
TrcClk
Trace interface clock. Operates at half the CPU core frequency.
O
3.3V LVTTL
TS0E
TS1E
Even trace execution status.
I/O
3.3V LVTTL
TS0O
TS1O
Odd trace execution status.
I/O
3.3V LVTTL
TS0:3
Trace status.
I/O
3.3V LVTTL
Table 6. Signal Functional Description (Sheet 3 of 7)
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 37 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
Signal Name
Description
I/O
Type
Notes
相關PDF資料 |
PDF描述 |
|---|---|
| PPC405EX-SpAfffTx | PowerPC 405EX Embedded Processor |
| PPC405EZ-CSAfffTx | PowerPC 405EZ Embedded Processor |
| PPC405GP-3BE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133C | Power PC 405GP Embedded Processor |
| PPC405GP-3KE133CZ | Power PC 405GP Embedded Processor |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PPC405EX-NPD400T | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-NPD533T | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-NPD600T | 制造商:AppliedMicro 功能描述:POWER ARCHITECTURE 405EP PROCESSOR USED FOR GENERAL NETWORKING 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-NSA333T | 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays |
| PPC405EX-NSA400T | 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays 制造商:AMCC 功能描述:AMCPPC405EX-NSA400T PCIE*2 WITHOUT ENGIN |
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