參數(shù)資料
型號(hào)： PPC405EX-NpAfffTx
廠商： Applied Micro Circuits Corp.
英文描述： PowerPC 405EX Embedded Processor
中文描述： 嵌入式處理器的PowerPC 405EX
文件頁(yè)數(shù)： 14/67頁(yè)
文件大?。?/td> 457K
代理商： PPC405EX-NPAFFFTX
PPC405EX – PowerPC 405EX Embedded Processor
14
AMCC Proprietary
Revision 1.09 - August 21, 2007
Preliminary Data Sheet
General Purpose I/O (GPIO) Controller
The GPIO controller enables multiplexing of module I/O pins with multiple functions within the chip. That is, a single
package pin can be assigned to multiple I/O functions. Which function the pin is assigned to is determined by
register bit settings controlled by software. This significantly reduces the number of package pins needed to
support multiple I/O groups.
Features include:
Up to 32 GPIOs available
– GPIOs are multiplexed with alternate functions
– If not in use for dedicated functions, I/Os are available as GPIOs
Direct control of all functions from registers programmed by means of OPB bus master accesses
Time multiplexing of controller outputs to module outputs
Programmable conversion of module outputs to open-drain outputs (enables sharing of active low outputs
externally)
Time multiplexing of module inputs to controller inputs
Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary between the
various sources of interrupts and the PPC405 processor.
Features include:
Ten external interrupt sources supported
Generate interrupt on level (high or low) or edge (rising or falling)
Programmable as synchronous (edge-capture or level-sensitive) or asynchronous (edge- or level-sensitive
triggering)
Each interrupt source/bit programmable as critical or non critical
DCR bus interface is 32 bits wide
Optional interrupt handler vector generation
– Programmable vector base address
– Programmable vector offset size
– Programmable interrupt priority ordering
Programmable polarity for all interrupt types
Interrupts of the same type do not need to be in contiguous bit positions
Status registers provide: current state of all interrupts, current state of enabled interrupts
Gigabit Ethernet
The Ethernet support provides two Gigabit (10/100/1000 Mbps) interfaces (GMII/RGMII ).
Features include:
ANSI/IEEE Std. 802.3 and IEEE 802.3u supplement compliant
Half-duplex and full-duplex supported
Receive FIFOs are 512 bytes with programmable thresholds
FCS control for transmit/receive packets
Multiple packet handling in transmit and receive FIFOs
Unicast, multicast, broadcast, and promiscuous address filtering
Two 256-bit hash filters for unicast and multicast frames
Automatic retransmission of collided frames
Runt frame rejection
Programmable inter-frame gap
IEEE 802.3x compliant for frame-based flow control mechanism, including self-assembled control frame
transmitting)
Wake-on-LAN and Power-over-Internet supported
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PPC405EX-NPD600T 制造商:AppliedMicro 功能描述:POWER ARCHITECTURE 405EP PROCESSOR USED FOR GENERAL NETWORKING 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 600 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays
PPC405EX-NSA333T 制造商:AppliedMicro 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays
PPC405EX-NSA400T 制造商:AMCC 功能描述:32 BIT POWERPC CORE, UP TO 533 MHZ, 2 PCIE, 2 10/100/1G ETHE - Trays 制造商:AMCC 功能描述:AMCPPC405EX-NSA400T PCIE*2 WITHOUT ENGIN
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