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參數(shù)資料
| 型號： | PowerPC 604e |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 4/34頁 |
| 文件大?。?/td> | 101K |
| 代理商： | POWERPC 604E |
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PowerPC 604e RISC Microprocessor Technical Summary
1.1.1 New Features of the PowerPC 604e Processor
Features of the 604e that are not implemented in the 604 are as follows:
Additional special-purpose registers
— HID1 provides four read-only PLL_CFG bits for indicating the processor/bus clock ratio.
— Three additional registers to support the performance monitor—MMCR1 is a second control
register that includes bits to support the use of two additional counter registers, PMC3 and
PMC4.
Instruction execution
— Separate units for branch and condition register (CR) instructions. The BPU is now split into a
CR logical unit and a branch unit, which makes it possible for branch instructions to execute
and resolve before preceding CR logical instructions. The 604e can still only dispatch one CR
logical or branch instruction per cycle, but it can execute both branch and CR logical
instructions at the same time.
— Branch correction in decode stage. Branch correction in the decode stage can now predict
branches whose target is taken from the count or link registers if no updates of the count and
link register are pending. This saves at least one cycle on branch correction when the Move to
Special-Purpose Register (
mtspr
) instruction can be sufficiently separated from the branch that
uses the special-purpose register (SPR) as a target address.
— Ability to disable the branch target address cache (BTAC)—HID0[30] has been defined to
allow the BTAC to be disabled. When HID0[30] is set, the BTAC contents are invalidated and
the BTAC behaves as if it were empty. New entries cannot be added until the BTAC is enabled.
Improvements to cache implementation
— 32-Kbyte split data and instruction caches. Like the 604, both caches are four-way set
associative; however, each cache has twice as many sets, logically separated into 128 sets of
odd lines and 128 sets of even lines.
— Data cache line-fill buffer forwarding. In the 604 only the critical double word of a burst
operation was made available to the requesting unit at the time it was burst into the line-fill
buffer. Subsequent data was unavailable until the cache block was filled. On the 604e,
subsequent data is also made available as it arrives in the line-fill buffer.
— Additional cache copyback buffers. The 604e implements three copyback write buffers (as
opposed to one in the 604). Having multiple copyback buffers provides the ability for certain
instructions to take fuller advantage of the pipelined system bus to provide more efficient
handling of cache copyback, block invalidate operations caused by the Data Cache Block Flush
(
dcbf
) instruction, and cache block clean operations resulting from the Data Cache Block Store
(
dcbst
) instruction.
— Coherency support for instruction fetching. Instruction fetching coherency is controlled by
HID0[23]. In the default mode, HID0[23] is 0, GBL is not asserted for instruction accesses, as
is the case with the 604. If the bit is set, and instruction translation is enabled (MSR[IR] = 1),
the GBL signal is set to reflect the M bit for this page or block. If instruction translation is
disabled (MSR[IR] = 0), the GBL
signal is asserted.
System interface operation
— The 604e has the same pin configuration as the 604; however, on the 604e Vdd and AVdd must
be tied to 2.5 Vdc and OVdd must be tied to 3.3 Vdc. The 604e uses split voltage planes, and
for replacement compatibility, 604/604e designs should provide both 2.5-V and 3.3-V planes
and the ability to tie those two planes together and disable the 2.5-V plane for operation with a
604.
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