參數(shù)資料
型號(hào)： PowerPC 604e
廠(chǎng)商： Motorola, Inc.
英文描述： 32-Bit Microprocessor(32位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 24/34頁(yè)
文件大小： 101K
代理商： POWERPC 604E
24
PowerPC 604e RISC Microprocessor Technical Summary
subdivision of the processor clock frequency. In the 604e. the time base frequency is 1/4th of the
bus clock frequency (as is the decrementer frequency). Counting is enabled by the Time Base
Enable (TBE) signal.
Block address translation (BAT) registers—The PowerPC architecture defines 16 BAT registers,
divided into four pairs of data BATs (DBATs) and four pairs of instruction BATs (IBATs).
Data address breakpoint register (DABR)—This register, defined as optional by the PowerPC
architecture, can be used to cause a breakpoint exception to occur if a specified data address is
encountered.
The 604e includes the following registers not defined by the PowerPC architecture:
Instruction address breakpoint register (IABR)—This register can be used to cause a breakpoint
exception to occur if a specified instruction address is encountered.
Hardware implementation-dependent register 0 (HID0)—This register is used to control various
functions within the 604e, such as enabling checkstop conditions, and locking, enabling, and
invalidating the instruction and data caches. Additional bits defined in the HID0 register disable the
BTAC, control whether coherency is maintained for instruction fetches, and for disabling the
default precharge values for the shared (SHD) and address retry (ARTRY) signals.
Hardware implementation-dependent register 1 (HID1)—This register, which is not implemented
in the 604, is used to display the PLL configuration.
Processor identification register (PIR)—The PIR is a supervisor-level register that has a right-
justified, four-bit field that holds a processor identification tag used to identify a particular 604e.
This tag is used to identify the processor in multiple-master implementations.
Performance monitor counter registers (PMC1–PMC4). The counters are used to record the number
of times a certain event has occurred. PMC3 and PMC4 are not implemented in the 604.
Performance monitor control registers (MMCR0 and MMCR1)—These registers are used for
enabling various performance monitoring interrupt conditions and establishes the function of the
counters. MMCR1 is not implemented in the 604.
Sampled instruction address and sampled data address registers (SIA and SDA)—These registers
hold the addresses for instruction and data used by the performance monitoring interrupt.
Note that while it is not guaranteed that the implementation of HID registers is consistent among PowerPC
processors, other processors may be implemented with similar or identical HID registers.
2.1.2 Instruction Set and Addressing Modes
The following subsections describe the PowerPC instruction set and addressing modes in general.
2.1.2.1 PowerPC Instruction Set and Addressing Modes
All PowerPC instructions are encoded as single-word (32-bit) opcodes. Instruction formats are consistent
among all instruction types, permitting efficient decoding to occur in parallel with operand accesses. This
fixed instruction length and consistent format greatly simplifies instruction pipelining.
2.1.2.1.1 Instruction Set
The 604e implements the entire PowerPC instruction set (for 32-bit implementations) and most optional
PowerPC instructions. The PowerPC instructions can be grouped into the following general categories:
Integer instructions—These include computational and logical instructions.
— Integer arithmetic instructions
— Integer compare instructions
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