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參數(shù)資料
| 型號： | PowerPC 604e |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 26/34頁 |
| 文件大?。?/td> | 101K |
| 代理商： | POWERPC 604E |
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26
PowerPC 604e RISC Microprocessor Technical Summary
— The TLB Synchronize (
tlbsync
) instruction ensures that all
tlbie
instructions previously
executed by the processor that issued the
tlbsync
instruction have completed.
Processor control instructions—These instructions are used for synchronizing memory accesses
and managing caches, TLBs, and segment registers. These instructions include Move to/from
Special-Purpose Register instructions (
mtspr
and
mfspr
).
Memory/cache control instructions—These instructions provide control of caches, TLBs, and
segment registers.
— User- and supervisor-level cache instructions
— Segment register manipulation instructions
— Translation lookaside buffer management instructions
Optional instructions—the 604e implements the following optional instructions:
— The
eciwx
/
ecowx
instruction pair
— The TLB Synchronize (
tlbsync
) instruction
— Optional graphics instructions:
– Store Floating-Point as Integer Word Indexed (
stfiwx
)
– Floating Reciprocal Estimate Single (
fres
)
– Floating Reciprocal Square Root Estimate (
frsqrte
)
– Floating Select (
fsel
)
Note that this grouping of the instructions does not indicate which execution unit executes a particular
instruction or group of instructions.
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The PowerPC
architecture uses instructions that are four bytes long and word-aligned. It provides for byte, half-word, and
word operand loads and stores between memory and a set of 32 GPRs. It also provides for word and double-
word operand loads and stores between memory and a set of 32 FPRs.
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register, modified,
and then written back to the target location with specific store instructions.
PowerPC processors follow the program flow when they are in the normal execution state. However, the
flow of instructions can be interrupted directly by the execution of an instruction or by an asynchronous
event. Either kind of exception may cause one of several components of the system software to be invoked.
2.1.2.1.2 Calculating Effective Addresses
The effective address (EA) is the
32-bit address computed by the processor when executing a memory
access or branch instruction or when fetching the next sequential instruction.
The PowerPC architecture supports two simple memory addressing modes:
EA = (
r
A|0) + offset (including offset = 0) (register indirect with immediate index)
EA = (
r
A|0) +
r
B (register indirect with index)
These simple addressing modes allow efficient address generation for memory accesses. Calculation of the
effective address for aligned transfers occurs in a single clock cycle.
For a memory access instruction, if the sum of the effective address and the operand length exceeds the
maximum effective address, the storage operand is considered to wrap around from the maximum effective
address to effective address 0.
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|---|---|
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| PPC7447RX867NB | PPC7457RX1000NB |
| PPC7457RX1000NB | PPC7457RX1000NB |
| PPC7457RX600NB | PPC7457RX1000NB |
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