參數(shù)資料
型號(hào)： PowerPC 604e
廠商： Motorola, Inc.
英文描述： 32-Bit Microprocessor(32位微處理器)
中文描述： 32位微處理器（32位微處理器）
文件頁(yè)數(shù)： 23/34頁(yè)
文件大小： 101K
代理商： POWERPC 604E
PowerPC 604e RISC Microprocessor Technical Summary
23
2.1.1.6 Segment Registers (SRs)
For memory management, 32-bit PowerPC implementations use sixteen 32-bit segment registers (SRs).
2.1.1.7 Special-Purpose Registers (SPRs)
The PowerPC operating environment architecture defines numerous special-purpose registers that serve a
variety of functions, such as providing controls, indicating status, configuring the processor, and performing
special operations. Some SPRs are accessed implicitly as part of executing certain instructions. All SPRs
can be accessed by using the move to/from special purpose register instructions,
mtspr
and
mfspr
.
In the 604e, all SPRs are 32 bits wide.
2.1.1.8 User-Level SPRs
The following SPRs are accessible by user-level software:
Link register (LR)—The link register can be used to provide the branch target address and to hold
the return address after branch and link instructions. The LR is 32 bits wide.
Count register (CTR)—The CTR is decremented and tested automatically as a result of branch and
count instructions. The CTR is 32 bits wide.
XER—The 32-bit XER contains the integer carry and overflow bits.
The time base registers (TBL and TBU) can be read by user-level software, but can be written to
only by supervisor-level software.
2.1.1.9 Supervisor-Level SPRs
The 604e also contains SPRs that can be accessed only by supervisor-level software. These registers consist
of the following:
The 32-bit DSISR defines the cause of data access and alignment exceptions.
The data address register (DAR) is a 32-bit register that holds the address of an access after an
alignment or DSI exception.
Decrementer register (DEC) is a 32-bit decrementing counter that provides a mechanism for
causing a decrementer exception after a programmable delay. In the 604e, the decrementer
frequency is 1/4th of the bus clock frequency (as is the time base frequency).
The 32-bit SDR1 register specifies the page table format used in logical-to-physical address
translation for pages.
The machine status save/restore register 0 (SRR0) is a 32-bit register that is used by the 604e for
saving the address of the instruction that caused the exception, and the address to return to when a
Return from Interrupt (
rfi
) instruction is executed.
The machine status save/restore register 1 (SRR1) is a 32-bit register used to save machine status
on exceptions and to restore machine status when an
rfi
instruction is executed.
SPRG0–SPRG3 registers are 32-bit registers provided for operating system use.
The external access register (EAR) is a 32-bit register that controls access to the external control
facility through the External Control In Word Indexed (
eciwx
) and External Control Out Word
Indexed (
ecowx
) instructions.
The processor version register (PVR) is a 32-bit, read-only register that identifies the version
(model) and revision level of the PowerPC processor.
The time base registers (TBL and TBU) together provide a 64-bit time base register. The registers
are implemented as a 64-bit counter, with the least-significant bit being the most frequently
incremented. The PowerPC architecture defines that the time base frequency be provided as a
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