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參數(shù)資料
| 型號： | PowerPC 604e |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數(shù)： | 13/34頁 |
| 文件大小： | 101K |
| 代理商： | POWERPC 604E |
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PowerPC 604e RISC Microprocessor Technical Summary
13
Address translations are enabled by setting bits in the MSR—MSR[IR] enables instruction address
translations and MSR[DR] enables data address translations.
The 604e’s MMUs support up to 4 Petabytes (252) of virtual memory and 4 Gigabytes (232) of physical
memory. The MMUs support block address translations, direct-store segments, and page translation of
memory segments. Referenced and changed status are maintained by the processor for each page to assist
implementation of a demand-paged virtual memory system.
Separate but identical translation logic is implemented for data accesses and for instruction accesses. The
604e implements two 128-entry, two-way set-associative translation lookaside buffers (TLBs), one for
instructions and one for data. These TLBs can be accessed simultaneously.
1.2.10 Cache Implementation
The PowerPC architecture does not define hardware aspects of cache implementations. For example,
whereas the 604e implements separate data and instruction caches (Harvard architecture), other processors
may use a unified cache, or no cache at all. The PowerPC architecture defines the unit of coherency as a
cache block, which for the 604e is a 32-byte (eight-word) line.
PowerPC implementations can control the following memory access modes on a page or block basis:
Write-back/write-through mode
Caching-inhibited mode
Memory coherency
Guarded memory (prevents access for out-of-order execution)
1.2.10.1 Instruction Cache
The 604e’s 32-Kbyte, four-way set-associative instruction cache is physically indexed. Within a single
cycle, the instruction cache provides up to four instructions.
The 604e provides coherency checking for instruction fetches. Instruction fetching coherency is controlled
by a HID0[23]. In the default mode, HID0[23] is 0, the GBL signal is not asserted for instruction accesses
on the bus, as is the case with the 604. If the bit is set and instruction translation is enabled (MSR[IR] = 1),
the GBL signal is set to reflect the M bit for this page or block. If HID0[23] is set and instruction translation
is disabled (MSR[IR] = 0), the GBL
signal is asserted and coherency is maintained in the instruction cache.
The PowerPC architecture defines a special set of instructions for managing the instruction cache. The
instruction cache can be invalidated entirely or on a cache-block basis. The instruction cache can be disabled
and invalidated by setting the HID0[16] and HID0[20] bits, respectively. The instruction cache can be
locked by setting HID0[18].
1.2.10.2 Data Cache
The 604e’s data cache is a 32-Kbyte, four-way set associative cache. It is a physically-indexed,
nonblocking, write-back cache with hardware support for reloading on cache misses. Within one cycle, the
data cache provides double-word access to the LSU.
Note that the 604e provides additional support for data cache line-fill buffer forwarding. In the 604 only the
critical double word of a burst operation was made available to the requesting unit at the time it was burst
into the line-fill buffer. Subsequent data was unavailable until the cache block was filled. On the 604e,
subsequent data is also made available as it arrives in the line-fill buffer.
The 604e implements three copyback write buffers (as opposed to one in the 604). Having multiple
copyback buffers provides the ability for certain instructions to take fuller advantage of the pipelined system
bus to provide more efficient handling of cache copyback, block invalidate operations caused by the data
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