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參數資料
| 型號： | PowerPC 604e |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32-Bit Microprocessor(32位微處理器) |
| 中文描述： | 32位微處理器（32位微處理器） |
| 文件頁數： | 10/34頁 |
| 文件大?。?/td> | 101K |
| 代理商： | POWERPC 604E |
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PowerPC 604e RISC Microprocessor Technical Summary
The 512-entry BHT provides two bits per entry, indicating four levels of dynamic prediction—strongly not-
taken, not-taken, taken, and strongly taken. The history of a branch’s direction is maintained in these two
bits. Each time a branch is taken the value is incremented (with a maximum value of three meaning strongly-
taken); when it is not taken, the bit value is decremented (with a minimum value of zero meaning strongly
not-taken). If the current value predicts taken and the next branch is taken again, the BHT entry then predicts
strongly taken. If the next branch is not taken, the BHT then predicts taken.
The dispatch logic also allocates each instruction to the appropriate execution unit. A reorder buffer (ROB)
entry is allocated for each instruction, and dependency checking is done between the instructions in the
dispatch queue. The rename buffers are searched for the operands as the operands are fetched from the
register file. Operands that are written by other instructions ahead of this one in the dispatch queue are given
the tag of that instruction’s rename buffer; otherwise, the rename buffer or register file supplies either the
operand or a tag. As instructions are dispatched, the fetch unit is notified that the dispatch queue can be
updated with more instructions.
1.2.4 Branch Processing Unit (BPU)
The BPU handles prediction and recovery for branch instructions. All branches, including unconditional
branches, are placed in a two-entry reservation station until conditions are resolved and they can be
executed. At that point, branch instructions are executed in order and the completion unit is notified whether
the prediction was correct.
Unlike the 604, the 604e has a separate unit for executing condition register logical instructions, which
makes it possible for branch instructions to execute and resolve before a preceding CR logical instruction.
The 604e can still only dispatch one CR logical or branch instruction per cycle, but it can execute both
branch and CR logical instructions at the same time.
Branch correction in the decode stage in the 604e can predict branches whose target is taken from the count
or link registers if no updates of the count and link register are pending. This saves at least one cycle on
branch correction when the
mtspr
instruction can be sufficiently separated from the branch that uses the
SPR as a target address.
HID0[30] has been defined to allow the BTAC to be disabled. When HID0[30] is set, the BTAC contents
are invalidated and that BTAC behaves as if it were empty. New entries cannot be added until the BTAC is
enabled.
The BPU shares a dispatch bus with the condition register.
1.2.5 Condition Register Unit (CRU)
Condition register logical instructions are executed by the CRU, which shares the dispatch bus with the
BPU. The CRU has its own two-entry reservation station. The 604e can still only dispatch one CR logical
or branch instruction per cycle, but it can execute both branch and CR logical instructions at the same time.
1.2.6 Completion Unit
The completion unit retires executed instructions from the reorder buffer (ROB) in the completion unit and
updates register files and control registers. The completion unit recognizes exception conditions and
discards any operations being performed on subsequent instructions in program order. The completion unit
can quickly remove instructions from a mispredicted branch, and the decode/dispatch unit begins
dispatching from the correct path.
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