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參數(shù)資料
| 型號： | PM5352-B1 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 61/77頁 |
| 文件大?。?/td> | 901K |
| 代理商： | PM5352-B1 |
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PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
57
9
TEST FEATURES DESCRIPTION
Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all
digital output pins and the data bus to be held in a high-impedance state.
This test feature may be used for board testing.
Test mode registers are used to apply test vectors during production
testing of the S/UNI-STAR. Test mode registers (as opposed to normal
mode registers) are selected when TRS (A[10]) is high.
Test mode registers may also be used for board testing. When all of the
TSBs within the S/UNI-STAR are placed in test mode 0, device inputs may
be read and device outputs may be forced via the microprocessor
interface (refer to the section "Test Mode 0" for details).
In addition, the S/UNI-STAR also supports a standard IEEE 1149.1 five-
signal JTAG boundary scan test port for use in board testing. All digital
device inputs may be read and all digital device outputs may be forced via
the JTAG test port.
Table 2: Test Mode Register Memory Map
Address
0x000-0x3FF
0x400
0x401-0x7FF
Register
Normal Mode Registers
Master Test Register
Reserved For Test
9.1 Master Test Register
Notes on Test Mode Register Bits:
1. Writing values into unused register bits has no effect. However, to
ensure software compatibility with future, feature-enhanced versions of
the product, unused register bits must be written with logic zero.
Reading back unused bits can produce either a logic one or a logic
zero; hence, unused register bits should be masked off by software
when read.
2. Writable test mode register bits are not initialized upon reset unless
otherwise noted.
This Material Copyrighted by Its Respective Manufacturer
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| PM5352-BI | 制造商:PMC 制造商全稱:PMC 功能描述:SATURN USER NETWORK INTERFACE 155 (STAR) |
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