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| 型號： | PM5352-B1 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 15/77頁 |
| 文件大小： | 901K |
| 代理商： | PM5352-B1 |
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PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
11
6
PIN DESCRIPTION
6.1 Line Side Interface Signals
Pin Name
Type
Pin
No.
Function
REFCLK
Input
AC5
The reference clock input (REFCLK) must provide a
jitter-free 19.44 MHz reference clock. It is used as
the reference clock by both clock recovery and
clock synthesis circuits.
When the WAN Synchronization controller is used,
REFCLK is supplied using a VCXO. In this
application, the transmit direction can be looped
timed to any of the line receivers in order to meet
wander transfer and holdover requirements.
.
RXD+
RXD-
Differential
PECL
inputs
AA1
Y2
The receive differential data inputs (RXD+, RXD-)
contain the NRZ bit serial receive stream. The
receive clock is recovered from the RXD+/- bit
stream. Please refer to the Operation section for a
discussion of PECL interfacing issues.
SD
Single-
Ended
PECL
Input
W3
The Signal Detect pin (SD) indicates the presence
of valid receive signal power from the Optical
Physical Medium Dependent Device. A PECL high
indicates the presence of valid data and a PECL
low indicates a loss of signal. It is mandatory that
SD be terminated into the equivalent network that
RXD+/- is terminated into.
.
RCLK
Output
AB14
The receive byte clock (RCLK) provides a timing
reference for the S/UNI-STAR receive outputs.
RCLK is a divide by eight of the recovered line rate
clock (19.44 MHz).
.
This Material Copyrighted by Its Respective Manufacturer
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