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參數(shù)資料
| 型號： | PM5352-B1 |
| 英文描述： | Interface IC |
| 中文描述： | 接口IC |
| 文件頁數(shù)： | 49/77頁 |
| 文件大?。?/td> | 901K |
| 代理商： | PM5352-B1 |
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PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
45
7
MICROPROCESSOR INTERFACE
The microprocessor interface block provides normal and test mode
registers, and the logic required to connect to the microprocessor
interface. The normal mode registers are required for normal operation,
and test mode registers are used to enhance the testability of the
S/UNI-STAR. The register set is accessed as shown in Table 1. In the
following section every register is documented and identified using the
register number (REG #).. Addresses that are not shown are not used and
must be treated as Reserved.
Table 1: Register Memory Map
REG
#
00
01
02
03
04
05
Address
A[10:0]
000
001
002
003
004
305
Description
S/UNI-STAR Master Reset and Identity
S/UNI-STAR Master Configuration
S/UNI-STAR Master System Interface Config
S/UNI-STAR Master Clock Monitor
S/UNI-STAR Master Interrupt Status
S/UNI-STAR Channel Reset and Performance
Monitoring Update
S/UNI-STAR Channel Configuration
S/UNI-STAR Channel Control
S/UNI-STAR Channel Control Extensions
Reserved
S/UNI-STAR Channel Interrupt Status 1
S/UNI-STAR Channel Interrupt Status 2
CSPI Control and Status (Clock Synthesis)
Reserved
CRSI Control and Status (Clock Recovery)
Reserved
RSOP Control/Interrupt Enable
RSOP Status/Interrupt Status
RSOP Section BIP-8 LSB
RSOP Section BIP-8 MSB
TSOP Control
TSOP Diagnostic
Reserved
Reserved
RLOP Control/Status
RLOP Interrupt Enable/Status
RLOP Line BIP-24 LSB
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
206
307
308
309
30A
30B
00C
00D
30E
30F
310
311
312
313
314
315
316
317
318
319
31A
This Material Copyrighted by Its Respective Manufacturer
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