參數(shù)資料
型號: PM5352-B1
英文描述: Interface IC
中文描述: 接口IC
文件頁數(shù): 5/77頁
文件大小: 901K
代理商: PM5352-B1
PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
1
1
FEATURES
1.1 General
Single chip ATM User-Network Interface operating at 155.52 Mbit/s.
Implements the ATM Forum User Network Interface Specification and
the ATM physical layer for Broadband ISDN according to CCITT
Recommendation I.432.
Implements the Point-to-Point Protocol (PPP) over SONET/SDH
specification according to RFC 1619/1662 of the PPP Working Group
of the Internet Engineering Task Force (IETF).
Processes duplex 155.52 Mbit/s STS-3c (STM-1) data streams with
on-chip clock and data recovery and clock synthesis.
Exceeds Bellcore GR-253-CORE jitter tolerance and intrinsic jitter
criteria.
Exceeds Bellcore GR-253-CORE jitter transfer and phase variation
criteria.
Provides control circuitry required to exceed Bellcore GR-253-CORE
WAN clocking requirements related to wander transfer, holdover and
long term stability when using an external VCXO.
Compatible with ATM Forum’s Utopia Level 2 Specification with Multi-
PHY addressing and parity support.
Implements the POS-PHY 16-bit System Interface for Packet over
SONET/SDH (POS) applications. This system interface is similar to
Utopia Level 2, but adapted to packet transfer. Both byte-level and
packet-level transfer modes are supported.
Provides a standard 5 signal IEEE 1149.1 JTAG test port for boundary
scan board test purposes.
Provides a generic 8-bit microprocessor bus interface for configuration,
control, and status monitoring.
Low power 3.3V CMOS with PECL and TTL compatible inputs and
CMOS/TTL outputs, with 5V tolerance inputs (system side interface is
3.3V only).
This Material Copyrighted by Its Respective Manufacturer
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