參數(shù)資料
型號: PM5352-B1
英文描述: Interface IC
中文描述: 接口IC
文件頁數(shù): 48/77頁
文件大?。?/td> 901K
代理商: PM5352-B1
PM5352 S/UNI STAR
DATA SHEET
PMC-1990421
ISSUE 2
SATURN USER NETWORK INTERFACE 155 (STAR)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
44
3. It is mandatory that every ground pin (VSS) be connected to the printed
circuit board ground plane to ensure a reliable device operation.
4. It is mandatory that every power pin (VDD) be connected to the printed
circuit board power plane to ensure a reliable device operation.
5. All analog power and ground can be sensitive to noise. They must be
isolated from the digital power and ground. Care must be taken to
decouple these pins from each other and all other analog power and
ground pins.
6. Due to ESD protection structures in the pads it is necessary to exercise
caution when powering a device up or down. ESD protection devices
behave as diodes between power supply pins and from I/O pins to power
supply pins. Under extreme conditions it is possible to blow these ESD
protection devices or trigger latch up.
Please adhere to the
recommended power supply sequencing as described in the
OPERATION section of PM5351 S/UNI-TETRA datasheet
.
7. Some device pins can be made 5V tolerant by connecting the BIAS pins
to a 5V power supply, while some other pins are 3.3V only. In summary,
the system interface (ATM or POS) is 3.3V only while the microprocessor
interface, SONET and line interfaces are 5V tolerant.
3.3V only I/O’s:
RDAT[15:0], RSOC/RSOP, RPRTY, RENB, REOP, RMOD, RERR, RVAL,
TDAT[15:0], TSOC/TSOP, TPRTY, TENB, TEOP, TMOD, TERR,
RCA/RPA, DRCA/DRPA, TCA/PTPA, STPA, DTCA/DTPA,
RADR[3:0], TADR[3:0], PHY_OEN
5V tolerant I/O’s:
REFCLK,
RCLK, RFPO, RALRM,
TCLK, TFPO, TFPI,
RSD, RSDCLK, TSD, TSDCLK. RLD, RLDCLK, TLD, TLDCLK.,
D[7:0], A[10:0], WRB, RDB, CSB, RSTB, INTB, ALE,
TRSTB, TCK, TMS, TDI, TDO,
This Material Copyrighted by Its Respective Manufacturer
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