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參數(shù)資料
| 型號： | PLX9656 |
| 英文描述： | I/O Accelerator|PCI9656 Data Book Corrections |
| 中文描述： | I / O加速器| PCI9656數(shù)據(jù)手冊更正 |
| 文件頁數(shù)： | 4/28頁 |
| 文件大?。?/td> | 162K |
| 代理商： | PLX9656 |
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12/19/2002
- 4 -
9656-SIL-DC1-P0-.96
3.
EEDI/EEDO Pull-Up When Local Processor Present But EEPROM Not
Present
When using the PCI 9656, if initialization is to be performed by a Local Bus master and
no serial EEPROM is present, the EEDI/EEDO pin must
not
be pulled down. This is true
for both the PCI 9656AD and the PCI 9656BA. The description in the Blue Book
regarding this is vague.
Tables 2-18 and 4-18 of the Blue Book make no mention of a pull-up or pull-down resistor on the
EEDI/EEDO pin when a Local Processor is present but an EEPROM is not present. The correct
requirement is that the EEDI/EEDO pin must be either be left floating or pulled up with a 1K-ohm
or greater value resistor when an EEPROM is not present. In any case, the pin must
not
be pulled
down.
The following shows the corrected entry of Tables 2-18 and 4-18:
Table 1. Serial EEPROM Guidelines
Local
Processor
Serial
EEPROM
System Boot Condition
…
Present
None
The Local Processor programs the PCI 9656 registers, then sets the
Local Init Status bit (LMISC1[2] = 1).
A 1K ohm or greater pull-up resistor on EEDI/EEDO is recommended,
but not required. The EEDI/EEDO pin already has an internal pull-up
(ref. Table 12-1).
Note:
Some systems may avoid configuring devices that do not
complete configuration accesses within 2
25
PCI clocks after RST# has
been de-asserted. In addition, some systems may hang if Direct Slave
reads and writes are immediately retried. The value of the Direct Slave
Retry Delay Clocks (LBRD0[31:28]) may resolve the hang by delaying
assertion of the STOP# signal by the PCI 9656.
…
4.
Updated Electrical Specifications
The following table updates Blue Book Table 13-5 for both the PCI 9656AD and the PCI
9656BA. Changes from the Blue Book are underlined.
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