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參數(shù)資料
| 型號： | PLX9656 |
| 英文描述： | I/O Accelerator|PCI9656 Data Book Corrections |
| 中文描述： | I / O加速器| PCI9656數(shù)據(jù)手冊更正 |
| 文件頁數(shù)： | 14/28頁 |
| 文件大?。?/td> | 162K |
| 代理商： | PLX9656 |
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12/19/2002
- 14 -
9656-SIL-DC1-P0-.96
The following figure shows the PCI 9656BA ALE output delay timing for any Processor/Local Bus
clock rate. It replaces Figure 13-3 in the Blue Book for the PCI 9656BA silicon. LC
HIGH
is the time
in ns that the Processor/Local Bus clock is high. (
Note.
When two times are given like x/y ns, x ns
is the minimum value and y ns is the maximum value.)
ALE
Local Clock
1.5V
LC
HIGH
LC
HIGH
+14.8/14.9 ns (33 MHz)
LC
HIGH
+6.8/6.9 ns (66 MHz)
3.4/6.9 ns
3.6/7.0 ns
3.0/6.4 ns
3.0/6.4 ns
1.5V
Address Bus
Figure 4. PCI 9656BA ALE Output Delay to the Local Clock
10. M Mode LA30 & LA 31 Pin Outs
Description:
The Blue Book Table 14-3 pin outs for pins P19 and P20 are indicated incorrectly. The M
Mode LA31 and LA30 signals are swapped. This is true for both the PCI 9656AD and the
PCI 9656BA.
Blue Book Table 14-3 indicates that pin P19 is “LA31 (M), LBE1# (C, J)” and pin P20 is “LA30
(M), LBE0# (C, J)”. This is incorrect.
For the PCI 9656AD and PCI 9656BA, pin P19 is “LA30 (M), LBE1# (C, J)” and pin P20 is “LA31
(M), LBE0# (C, J)”.
Note that in Table 12-10 the pin numbers for LA30 and LA31 are indicated correctly.
11. AC Timing
Description:
PLX had conducted exhaustive static timing analysis (STA) of the PCI 9656AD and PCI
9656BA silicon. The following six tables contain the results of that analysis and replace
tables 13-6, 13-7, 13-8, and 13-9 in the Blue Book.
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