參數(shù)資料
型號： PLX9656
英文描述： I/O Accelerator|PCI9656 Data Book Corrections
中文描述： I / O加速器| PCI9656數(shù)據(jù)手冊更正
文件頁數(shù)： 15/28頁
文件大?。?/td> 162K
代理商： PLX9656
12/19/2002
- 15 -
9656-SIL-DC1-P0-.96
Table 11. C Mode Local Bus Input AC Timing Specifications
Signals
(Synchronous Inputs)
(V
CC
= 3.0V, T
a
= 85°C)
Blue Book
4.5 ns
BIGEND#
4.5 ns
BLAST#
4.5 ns
BREQi
4.5 ns
BTERM#
4.5 ns
CCS#
4.5 ns
DMPAF/
EOT#
4.5 ns
DP[3:0]
4.5 ns
DREQ[1:0]#
4.5 ns
LA[31:2]
4.5 ns
LBE[3:0]#
4.5 ns
LD[31:0]
4.5 ns
LHOLDA
4.5 ns
LW/R#
4.5 ns
READY#
4.5 ns
USERi/LLOCKi#
4.5 ns
WAIT#
4.5 ns
Input Clocks
Local Clock Input Frequency
PCI Clock Input Frequency
T
T
(V
CC
= 3.0V, T
a
= 85°C)
Blue Book AD STA
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
Max
66 MHz
66 MHz
ADS#
AD STA
4.8 ns
4.8 ns
4.0 ns
1.7 ns
4.8 ns
1.7 ns
4.7 ns
2.0 ns
4.4 ns
4.0 ns
4.6 ns
4.9 ns
4.2 ns
5.0 ns
4.7 ns
2.4 ns
4.7 ns
Min
0 MHz
0 MHz
BA STA
2.1 ns
4.0 ns
3.4 ns
0.3 ns
4.0 ns
2.9 ns
4.2 ns
2.9 ns
3.3 ns
3.4 ns
3.6 ns
3.1 ns
2.5 ns
3.5 ns
4.0 ns
2.9 ns
4.0 ns
BA STA
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
1 ns
Table 12. C Mode Local Bus Output AC Timing Specifications
Signals
(Synchronous Outputs)
Blue Book
9ns
BLAST#
BREQo
BTERM#
DACK[1:0]#
DMPAF
/EOT#
DP[3:0]
LA[31:2]
LBE[3:0]#
LD[31:0]
LHOLD
LSERR#
LW/R#
READY#
USERo/LLOCKo#
WAIT#
Output T
(C
L
= 50pF, V
CC
= 3.0V, T
a
= 85°C)
AD
1
STA
7.6 ns
7.6 ns
9.5 ns
8.3 ns
7.6 ns
8.5 ns
7.9 ns
8.0 ns
7.6 ns
7.8 ns
7.5 ns
10.2 ns
7.6 ns
9.0 ns
7.6 ns
7.6 ns
ADS#
BA
2
STA
6.3 ns
6.3 ns
6.8 ns
6.8 ns
6.3 ns
6.6 ns
6.8 ns
6.8 ns
6.3 ns
6.4 ns
6.8 ns
7.5 ns
6.3 ns
7.2 ns
6.3 ns
6.4 ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
9ns
1.
On high-to-low transitions, output T
VALID
values increase/decrease by 23 ps for each increase/decrease of 1pF.
On low-to-high transitions, output T
VALID
values increase/decrease by 20 ps for each increase/decrease of 1pF.
2.
On high-to-low transitions, output T
VALID
values increase/decrease by 16 ps for each increase/decrease of 1pF.
On low-to-high transitions, output T
VALID
values increase/decrease by 20 ps for each increase/decrease of 1pF.
On high-to-low transitions, the slew rate at 50 pF loading is 1.93 V/ns typical; .94 V/ns worst case.
On low-to-high transitions, the slew rate at 50 pF loading is 1.15 V/ns typical; .70 V/ns worst case.
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