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參數(shù)資料
| 型號： | PLX9656 |
| 英文描述： | I/O Accelerator|PCI9656 Data Book Corrections |
| 中文描述： | I / O加速器| PCI9656數(shù)據(jù)手冊更正 |
| 文件頁數(shù)： | 13/28頁 |
| 文件大小： | 162K |
| 代理商： | PLX9656 |
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12/19/2002
- 13 -
9656-SIL-DC1-P0-.96
8.
Local Bus Pause Timer Count Must Be Even (MARBR[8] = 0)
The Blue Book includes a description of the Local Bus Pause Timer in the MARBR
register (Register Description 11-40). For the PCI 9656AD, the Local Bus Pause Timer
count must be even (MARBR[8] = 0). This restriction is not included in the Blue Book
description. For the PCI 9056BA, this count may be odd or even (MARBR[8] = 0 or 1).
The PCI 9656 includes a Local Bus Pause Timer (MARBR[15:8]) for specifying how long to stay
off of the Local Bus between transfers to/from the Local Bus during DMA.
For the PCI 9656AD, this count must be even (MARBR[8] = 0). Note that this counter is 0 after
reset, so the only time this correction is of concern is if the Local Bus Pause Timer count is ever
changed from its reset value.
For the PCI 9056BA, this count may be odd or even (MARBR[8] = 0 or 1).
9.
ALE Output Delay Timing For Any Local Bus Clock Rate
The Blue Book includes Figure 13-3 that shows the ALE output delay timing to the
Processor/Local Bus clock for a clock rate of 33MHz. It does not show the output delay
timing for other clock rates.
The following figure shows the PCI 9656AD ALE output delay timing for any Processor/Local Bus
clock rate. It replaces Figure 13-3 in the Blue Book for the PCI 9656AD silicon. LC
HIGH
is the time
in ns that the Processor/Local Bus clock is high. (
Note.
When two times are given like x/y ns, x ns
is the minimum value and y ns is the maximum value.)
ALE
Local Clock
Address Bus
1.5V
LC
HIGH
LC
HIGH
+15.1/15.4 ns (33 MHz)
LC
HIGH
+7.6/7.9 ns (66 MHz)
3.1/6.9 ns
2.9/6.5 ns
2.9/7.8 ns
2.9/7.8 ns
1.5V
Figure 3. PCI 9656AD ALE Output Delay to the Local Clock
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