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參數(shù)資料
| 型號： | PLX9656 |
| 英文描述： | I/O Accelerator|PCI9656 Data Book Corrections |
| 中文描述： | I / O加速器| PCI9656數(shù)據(jù)手冊更正 |
| 文件頁數(shù)： | 3/28頁 |
| 文件大?。?/td> | 162K |
| 代理商： | PLX9656 |
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12/19/2002
- 3 -
9656-SIL-DC1-P0-.96
The following text replaces sections 2.4.1.2 and 4.4.1.2 of the Blue Book. Note that these
sections of the Blue Book look very similar to what is below. The key difference is that the polarity
of USERi is incorrectly reversed in the Blue Book descriptions. Follow the polarity in the
description below. Changes from the Blue Book are underlined.
2.4.1.2/4.4.1.2 Local Initialization
As stated in
PCI r2.
2, Section 3.5.1.1:
“If the target is accessed during initialization-time, it is allowed to do any of the
following:
1. Ignore the request (except if it is a boot device). This results in a Master Abort.
2. Claim the access and hold in wait sates until it can complete the request, not to
exceed the end of initialization-time.
3. Claim the access and terminate with [PCI] Retry.”
The PCI 9656 supports Option 1 (
Initially Not Respond
), and Option 3 (
Initially Retry
),
above. For CompactPCI Hot Swap live insertion systems, the preferred method for
the silicon is usually not to respond to PCI Configuration accesses during
initialization. For legacy systems, Retries are usually preferred for compatibility
reasons. However, it is ultimately the designer’s choice of which option to use.
The PCI 9656 determines the option to use as follows:
The USERi pin is sampled at the rising edge RST# to determine the selected PCI
Bus response mode during local initialization. If USERi is low (through an external 1K
ohm pull-down resistor), the PCI 9656 does not respond to PCI activity until the
device’s Local Bus initialization is complete. This results in a Master Abort (the
preferred method for CompactPCI Hot Swap systems). If USERi is high (through an
external 1K—4.7K ohm pull-up resistor), the PCI 9656 responds to PCI accesses
with PCI Retry cycles until the device’s Local Bus initialization is complete. Local Bus
initialization is complete when the Local Init Status bit is set (LMISC1[2]=1).
The LMISC1[2] bit can be programmed in one of three ways:
1. By a Local Bus master writing a 1 directly to LMISC1[2].
2. By the serial EEPROM specifying a value of 1 for LMISC1[2] during a serial
EEPROM load.
3. If a Local Bus Master is not present and either a serial EEPROM is not present or
a blank serial EEPROM is present, the PCI 9656 reverts to its power on/reset
default register values and sets this bit. (Refer to Table 2-18 on page 2-9.)
During run time, USERi can be used as a general purpose input as described in the
Tables 12-10, 12-11, and 12-12, for the M, C, and J mode Local Bus pins.
Refer to Section 9, “CompactPCI Hot Swap” for specifics on using this feature in
PICMG 2.1, R2.0
systems.
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