參數(shù)資料
型號: PIP201-12M
廠商: NXP SEMICONDUCTORS
元件分類: 模擬信號調理
英文描述: SPECIALTY ANALOG CIRCUIT, PQCC68
封裝: 10 X 10 X 0.85 MM, PLASTIC, HVQFN-68
文件頁數(shù): 15/20頁
文件大?。?/td> 333K
代理商: PIP201-12M
Philips Semiconductors
PIP201-12M
DC to DC converter powertrain
Product data
Rev. 02 — 18 July 2002
4 of 21
9397 750 09833
Koninklijke Philips Electronics N.V. 2002. All rights reserved.
When the input voltage is LOW and current is owing in the inductor, the upper
MOSFET must be off and the lower MOSFET must be on. Current ows from the
power ground (VSSO), through the lower MOSFET and the inductor (Lout), to the
output.
Finally, when switching between states, both MOSFETs must not be on at the same
time.
7.2 MOSFET driver function
The input, output and gate drive waveforms are shown in Figure 4. When the input
voltage goes HIGH, the gate drive to the lower MOSFET immediately goes LOW. This
causes the output current to ow through the source-drain diode of the lower
MOSFET. This causes output voltage to fall from zero to approximately
0.7 V.
After a delay, if the input voltage is still HIGH, the gate drive to the upper MOSFET
goes HIGH. This causes the output voltage to rise to the output stage supply voltage,
VDDO.
When the input voltage goes LOW, the gate drive to the upper MOSFET immediately
goes LOW. The output voltage falls from VDDO, until it is clamped by the source-drain
diode of the synchronous FET at approximately
0.7 V.
After a delay, if the input voltage is still LOW, the gate drive to the lower MOSFET
goes HIGH. The lower MOSFET turns on, and the output voltage rises from
0.7 V to
zero.
7.3 Bootstrap diode
A bootstrap diode is integrated into the design of the PIP201-12M between VDDC and
CB.
Fig 4.
Input, output and gate drive waveforms of a synchronous DC to DC converter
output stage.
input voltage
output voltage
upper MOSFET
gate drive
lower MOSFET
gate drive
03ag35
delay
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相關代理商/技術參數(shù)
參數(shù)描述
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