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參數(shù)資料
| 型號： | PI7C8150 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 97/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 97 of 115
July 31, 2003 – Revision 1.031
Bit
Function
Type
Description
Controls PI7C8150B’s detection mechanism for matching memory
read retry cycles from the initiator on the secondary
0: exact matching for memory read retry cycles from initiator on the
secondary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the secondary interface
Reset to 0
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write retry cycles from the initiator on the primary interface
0: exact matching for non-posted memory write retry cycles from
initiator on the secondary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the secondary interface
Reset to 0
Reserved. Returns 0 when read. Reset to 0.
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the primary
interface
0: When accepting MEMWI command at the primary interface,
PI7C8150B converts MEMWI to MEMW command on the
secondary interface
1: Disconnects MEMWI command at aligned cache line boundaries
Controls PI7C8150B’s detection mechanism for matching non-posted
memory write and invalidate cycles from the initiator on the
secondary interface
0: When accepting MEMWI command at the secondary interface,
PI7C8150B converts MEMWI to MEMW command on the primary
interface
1: Disconnects MEMWI command at aligned cache line boundaries
Controls PI7C8150B’s ability to enable long requests for lock cycles
0: normal lock operation
1: enable long request for lock cycle
Reset to 0
Control’s PI7C8150B’s ability to enable the secondary bus to hold
requests longer.
0: internal secondary master will release REQ_L after FRAME_L
assertion
1: internal secondary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
Control’s PI7C8150B’s ability to hold requests longer at the Primary
Port.
0: internal Primary master will release REQ_L after FRAME_L
assertion
1: internal Primary master will hold REQ_L until there is no
transactions pending in FIFO or until terminated by target
Reset to 1
3
Secondary
MEMR
Command Alias
Enable
R/W
4
Secondary
MEMW
Command Alias
Enable
R/W
5:6
Reserved
R/O
7
Primary
MEMWI
Command Alias
Enable
R/W
8
Secondary
MEMWI
Command Alias
Enable
R/W
9
Enable Long
Request
R/W
10
Enable
Secondary To
Hold Request
Longer
R/W
11
Enable Primary
To Hold Request
Longer
R/W
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
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