參數(shù)資料
型號(hào)： PI7C8150
英文描述： PCI Bridge | 2-Port PCI-to-PCI Bridge
中文描述： PCI橋| 2端口PCI至PCI橋
文件頁(yè)數(shù)： 101/115頁(yè)
文件大?。?/td> 879K
代理商： PI7C8150
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 101 of 115
July 31, 2003 – Revision 1.031
15
BRIDGE BEHAVIOR
A PCI cycle is initiated by asserting the FRAME_L signal. In a bridge, there are a number
of possibilities. Those possibilities are summarized in the table below:
15.1
BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES
Initiator
Master on Primary
Target
Target on Primary
Response
PI7C8150B does not respond. It detects
this situation by decoding the address as
well as monitoring the P_DEVSEL_L for
other fast and medium devices on the
Primary Port.
PI7C8150B asserts P_DEVSEL_L,
terminates the cycle normally if it is able
to be posted, otherwise return with a retry.
It then passes the cycle to the appropriate
port. When the cycle is complete on the
target port, it will wait for the initiator to
repeat the same cycle and end with normal
termination.
PI7C8150B does not respond and the
cycle will terminate as master abort.
PI7C8150B does not respond.
Master on Primary
Target on Secondary
Master on Primary
Target not on Primary nor
Secondary Port
Target on the same
Secondary Port
Target on Primary or the
other Secondary Port
Master on Secondary
Master on Secondary
PI7C8150B asserts S_DEVSEL_L,
terminates the cycle normally if it is able
to be posted, otherwise returns with a
retry. It then passes the cycle to the
appropriate port. When cycle is complete
on the target port, it will wait for the
initiator to repeat the same cycle and end
with normal termination.
PI7C8150B does not respond.
Master on Secondary
Target not on Primary nor
the other Secondary Port
15.2
ABNORMAL TERMINATION (INITIATED BY BRIDGE
MASTER)
15.2.1
MASTER ABORT
Master abort indicates that when PI7C8150B acts as a master and receives no response
(i.e., no target asserts DEVSEL_L or S_DEVSEL_L) from a target, the bridge de-asserts
FRAME_L and then de-asserts IRDY_L.
15.2.2
PARITY AND ERROR REPORTING
Parity must be checked for all addresses and write data. Parity is defined on the P_PAR,
and S_PAR signals. Parity should be even (i. e. an even number of‘1’s) across AD, CBE,
and PAR. Parity information on PAR is valid the cycle after AD and CBE are valid. For
reads, even parity must be generated using the initiators CBE signals combined with the
相關(guān)PDF資料
PDF描述
PI7C8150-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150A PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150A-33 PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150B PCI Bridge | Asynchronous 2-Port PCI Bridge
PI7C8152A ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8150-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150A-33 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge
PI7C8150AMA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP
PI7C8150AMA-33 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP
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