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參數(shù)資料
| 型號： | PI7C8150 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 94/115頁 |
| 文件大小： | 879K |
| 代理商： | PI7C8150 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 94 of 115
July 31, 2003 – Revision 1.031
Bit
Function
Type
Description
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set.
1: P_SERR_L is not assert if this event occurs.
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer delayed write data after 2
attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
target abort when attempting to deliver posted write data.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it receives a
master abort when attempting to deliver posted write data.
0: P_SERR# is asserted if this event occurs and the SERR# enable bit
in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR# when it is unable to
transfer delayed write data after 2
attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Controls PI7C8150B’s ability to assert P_SERR_L when it is unable
to transfer any read data from the target after 2
attempts.
0: P_SERR_L is asserted if this event occurs and the SERR_L enable
bit in the command register is set
1: P_SERR_L is not asserted if this event occurs
Reset to 0
Reserved. Returns 0 when read. Reset to 0
1
Posted Write
Parity Error
R/W
2
Posted Write
Non-Delivery
R/W
3
Target Abort
During Posted
Write
R/W
4
Master Abort On
Posted Write
R/W
5
Delayed Write
Non-Delivery
R/W
6
Delayed Read –
No Data From
Target
R/W
7
Reserved
R/O
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
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