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參數(shù)資料
| 型號(hào)： | PI7C8150 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 54/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 54 of 115
July 31, 2003 – Revision 1.031
PI7C8150B does not have a hardware mechanism to guarantee data synchronization for
posted write transactions. Therefore, all posted write transactions must be followed by a
read operation, either from the device to the location just written (or some other location
along the same path), or from the device driver to one of the device registers.
6
ERROR HANDLING
PI7C8150B checks, forwards, and generates parity on both the primary and secondary
interfaces. To maintain transparency, PI7C8150B always tries to forward the existing
parity condition on one bus to the other bus, along with address and data. PI7C8150B
always attempts to be transparent when reporting errors, but this is not always possible,
given the presence of posted data and delayed transactions.
To support error reporting on the PCI bus, PI7C8150B implements the following:
!
PERR_L and SERR_L signals on both the primary and secondary interfaces
!
Primary status and secondary status registers
!
The device-specific P_SERR_L event disable register
This chapter provides detailed information about how PI7C8150B handles errors.
It also describes error status reporting and error operation disabling.
6.1
ADDRESS PARITY ERRORS
PI7C8150B checks address parity for all transactions on both buses, for all address and all
bus commands. When PI7C8150B detects an address parity error on the primary interface,
the following events occur:
!
If the parity error response bit is set in the command register, PI7C8150B does not
claim the transaction with P_DEVSEL_L; this may allow the transaction to terminate
in a master abort. If parity error response bit is not set, PI7C8150B proceeds normally
and accepts the transaction if it is directed to or across PI7C8150B.
!
PI7C8150B sets the detected parity error bit in the status register.
!
PI7C8150B asserts P_SERR_L and sets signaled system error bit in the status register,
if both the following conditions are met:
!
The SERR_L enable bit is set in the command register.
!
The parity error response bit is set in the command register.
When PI7C8150B detects an address parity error on the secondary interface, the following
events occur:
!
If the parity error response bit is set in the bridge control register, PI7C8150B does not
claim the transaction with S_DEVSEL_L; this may allow the transaction to terminate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
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