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參數(shù)資料
| 型號： | PI7C8150 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 78/115頁 |
| 文件大小： | 879K |
| 代理商： | PI7C8150 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 78 of 115
July 31, 2003 – Revision 1.031
are driven low for the duration of S_RESET_L assertion. All posted write and delayed
transaction data buffers are reset. Therefore, any transactions residing inside the buffers at
the time of secondary reset are discarded.
When S_RESET_L is asserted by means of the secondary reset bit, PI7C8150B remains
accessible during secondary interface reset and continues to respond to accesses to its
configuration space from the primary interface.
12.3
CHIP RESET
The chip reset bit in the diagnostic control register can be used to reset the PI7C8150B and
the secondary bus.
When the chip reset bit is set, all registers and chip state are reset and all signals are
tristated. S_RESET_L is asserted and the secondary reset bit is automatically set.
S_RESET_L remains asserted until a configuration write operation clears the secondary
reset bit and the serial clock mask has been shifted in. Within 20 PCI clock cycles after
completion of the configuration write operation, PI7C8150B’s reset bit automatically clears
and PI7C8150B is ready for configuration.
During reset, PI7C8150B is inaccessible.
13
SUPPORTED COMMANDS
The PCI command set is given below for the primary and secondary interfaces.
13.1
PRIMARY INTERFACE
P_CBE [3:0]
0000
Command
Interrupt
Acknowledge
Special Cycle
I/O Read
Action
Ignore
0001
0010
Do not claim. Ignore.
1. If address is within pass through I/O range, claim and pass
through.
2. Otherwise, do not pass through and do not claim for
internal access.
Same as I/O Read.
-----
-----
1. If address is within pass through memory range, claim and
pass through.
2. If address is within pass through memory mapped I/O
range, claim and pass through.
3. Otherwise, do not pass through and do not claim for
internal access.
Same as Memory Read.
-----
-----
0011
0100
0101
0110
I/O Write
Reserved
Reserved
Memory Read
0111
1000
1001
Memory Write
Reserved
Reserved
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
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