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參數(shù)資料
| 型號(hào)： | PI7C8150 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁(yè)數(shù)： | 23/115頁(yè) |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150 |
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PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 23 of 115
July 31, 2003 – Revision 1.031
!
PI7C8150B neither generates Type 0 configuration transactions on the primary PCI
bus nor responds to Type 0 configuration transactions on the secondary PCI buses.
3.2
SINGLE ADDRESS PHASE
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0], and
the bus command is driven on P_CBE[3:0]. PI7C8150B supports the linear increment
address mode only, which is indicated when the lowest two address bits are equal to zero.
If either of the lowest two address bits is nonzero, PI7C8150B automatically disconnects
the transaction after the first data transfer.
3.3
DEVICE SELECT (DEVSEL_L) GENERATION
PI7C8150B always performs positive address decoding (medium decode) when accepting
transactions on either the primary or secondary buses. PI7C8150B never does subtractive
decode.
3.4
DATA PHASE
The address phase of a PCI transaction is followed by one or more data phases. A data
phase is completed when IRDY_L and either TRDY_L or STOP_L are asserted. A
transfer of data occurs only when both IRDY_L and TRDY_L are asserted during the same
PCI clock cycle. The last data phase of a transaction is indicated when FRAME_L is de-
asserted and both TRDY_L and IRDY_L are asserted, or when IRDY_L and STOP_L are
asserted. See Section 3.8 for further discussion of transaction termination.
Depending on the command type, PI7C8150B can support multiple data phase PCI
transactions. For detailed descriptions of how PI7C8150B imposes disconnect boundaries,
see Section 3.5.4 for write address boundaries and Section 3.6.3 read address boundaries.
3.5
WRITE TRANSACTIONS
Write transactions are treated as either posted write or delayed write transactions. Table
3-2 shows the method of forwarding used for each type of write operation.
Table 3-2. Write Transaction Forwarding
Type of Transaction
Memory Write
Memory Write and Invalidate
Memory Write to VGA memory
I/O Write
Type 1 Configuration Write
Type of Forwarding
Posted (except VGA memory)
Posted
Delayed
Delayed
Delayed
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
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