- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C8150 PCI Bridge | 2-Port PCI-to-PCI Bridge PDF資料下載
參數(shù)資料
| 型號： | PI7C8150 |
| 英文描述： | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| 中文描述： | PCI橋| 2端口PCI至PCI橋 |
| 文件頁數(shù)： | 59/115頁 |
| 文件大?。?/td> | 879K |
| 代理商： | PI7C8150 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁當前第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁
PI7C8150B
2-PORT PCI-TO-PCI BRIDGE
ADVANCE INFORMATION
Page 59 of 115
July 31, 2003 – Revision 1.031
6.2.4
POSTED WRITE TRANSACTIONS
During downstream posted write transactions, when PI7C8150B responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
!
PI7C8150B asserts P_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
!
PI7C8150B sets the parity error detected bit in the status register of the primary
interface.
!
PI7C8150B captures and forwards the bad parity condition to the secondary bus.
!
PI7C8150B completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C8150B responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following events
occur:
!
PI7C8150B asserts S_PERR_L two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
!
PI7C8150B sets the parity error detected bit in the status register of the secondary
interface.
!
PI7C8150B captures and forwards the bad parity condition to the primary bus.
!
PI7C8150B completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target
(secondary) bus by the target’s assertion of S_PERR_L, the following events occur:
!
PI7C8150B sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
!
PI7C8150B asserts P_SERR_L and sets the signaled system error bit in the status
register, if all the following conditions are met:
!
The SERR_L enable bit is set in the command register.
!
The posted write parity error bit of P_SERR_L event disable register is not
set.
!
The parity error response bit is set in the bridge control register of the
secondary interface.
!
The parity error response bit is set in the command register of the primary
interface.
!
PI7C8150B has not detected the parity error on the primary (initiator) bus
which the parity error is not forwarded from the primary bus to the
secondary bus.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| PI7C8150-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150B | PCI Bridge | Asynchronous 2-Port PCI Bridge |
| PI7C8152A | ENHANCED 2- PORT TO PCI BRIDGE INTEL 21152 COMPORISON |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8150-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150A-33 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:PCI Bridge | 2-Port PCI-to-PCI Bridge |
| PI7C8150AMA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 208-Pin FQFP |
| PI7C8150AMA-33 | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 208-Pin FQFP |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。