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09/18/00 Rev 1.1
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PI7C7100
ADVANCE INFORMATION
13.2.34 Config Register 1: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)
This register is implemented but not being used internally.This register defines the base address of the primary
prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits
corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read
only and are set to 0h. The lower 20 address bits (19:0) are assumed to be 00000h.
13.2.35 Config Register 2: Primary Prefetchable Memory Base Register (Read/Write, bit 15-0; offset 44h)
This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20]
are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h.
13.2.36 Config Register 1: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)
This register is implemented but not being used internally.This register defines the upper limit address of the primary
prefetchable memory-mapped address range for forwarding the cycle through the bridge. The upper twelve bits
corresponding to address bits [31:20] are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read
only and are set to 0h. The lower 20 address bits (19:0) are assumed to be FFFFFh.
13.2.37 Config Register 2: Primary Prefetchable Memory Limit Register (Read/Write, bit 31-16; offset 44h)
This register is implemented but not being used internally. The upper twelve bits corresponding to address bits [31:20]
are read/write. The upper twelve bits are reset to 0000h. The lower four bits are read only and are set to 0h.
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13.2.38 Config Register 1 or 2: P_SERR# Event Disable Register (bit 7-0; offset 64h)
Note:
R/W - Read/Write, R/O - Read Only, R/WC - Read/ Write 1 to clear.