參數(shù)資料
型號： PI7C7100
廠商： Pericom Semiconductor Corp.
英文描述： 3-Port PCI Bridge
中文描述： 3端口PCI橋
文件頁數(shù)： 33/132頁
文件大小： 2559K
代理商： PI7C7100
25
09/18/00 Rev 1.1
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PI7C7100
ADVANCE INFORMATION
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Table 4-8. Responses to Posted Write Target Termination
Note that when a target retry or target disconnect is returned and posted write data associated with that transaction
remains in the write buffers, PI7C7100 initiates another write transaction to attempt to deliver the rest of the write data.
If there is a target retry, the exact same address will be driven as for the initial write transaction attempt. If a target
disconnect is received, the address that is driven on a subsequent write transaction attempt will be updated to reflect
the address of the current DWORD. If the initial write transaction is Memory-Write-and-Invalidate transaction, and a
partial delivery of write data to the target is performed before a target disconnect is received, PI7C7100 will use the
memory write command to deliver the rest of the write data. It is because an incomplete cache line will be transferred
in the subsequent write transaction attempt.
After the PI7C7100 makes 2
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(default) write transaction attempts and fails to deliver all posted write data associated with
that transaction, PI7C7100 asserts P_SERR# if the primary SERR# enable bit is set (bit 8 of command register for
secondary bus S1 or S2) and posted-write-non-delivery bit is not set. The posted-write-non-delivery bit is the bit 2 of
P_SERR# event disable register (offset 64h). PI7C7100 will report system error. See Section 7.4 for a discussion of system
error conditions.
4.8.3.3 Delayed Read Target Termination Response
When PI7C7100 initiates a delayed read transaction, the abnormal target responses can be passed back to the initiator.
Other target responses depend on how much data the initiator requests. Table 4–9 shows the response to each type
of target termination that occurs during a delayed read transaction.
PI7C7100 repeats a delayed read transaction until one of the following conditions is met:
PI7C7100 completes at least one data transfer.
PI7C7100 receives a master abort.
PI7C7100 receives a target abort.
PI7C7100 makes 2
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(default) read attempts resulting in a response of target retry.
Table 4-9. Responses to Delayed Read Target Termination
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相關(guān)PDF資料
PDF描述
PI7C7100CNA 3-Port PCI Bridge
PI7C7300 3-PORT PCI-to-PCI BRIDGE
PI7C7300A 3-PORT PCI-to-PCI BRIDGE
PI7C7300ANA 3-PORT PCI-to-PCI BRIDGE
PI7C8140A 2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C7100BNA 制造商:Pericom Semiconductor Corporation 功能描述:3 PORT PCI TO PCI
PI7C7100CNA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge
PI7C7300 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE
PI7C7300A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE
PI7C7300AEVB-3 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
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