參數(shù)資料
型號： PI7C7100
廠商： Pericom Semiconductor Corp.
英文描述： 3-Port PCI Bridge
中文描述： 3端口PCI橋
文件頁數(shù)： 32/132頁
文件大小： 2559K
代理商： PI7C7100
24
09/18/00 Rev 1.1
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4.8.3 Target Termination Received by PI7C7100
When PI7C7100 initiates a transaction on the target bus and the target responds with DEVSEL#, the target can end the
transaction with one of the following types of termination:
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
Table 4-7. Delayed Write Target Termination Response
After the PI7C7100 makes 2
24
(default) attempts of the same delayed write transaction on the target bus, PI7C7100 asserts
P_SERR# if the SERR# enable bit (bit 8 of command register for secondary bus S1 or S2) is set and the delayed-write-
non-delivery bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable register (offset 64h).
PI7C7100 will report system error. See Section 7.4 for a description of system error conditions.
4.8.3.2 Posted Write Target Termination Response
When PI7C7100 initiates a posted write transaction, the target termination cannot be passed back to the initiator. Table
4–8 shows the response to each type of target termination that occurs during a posted write transaction.
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Normal termination (upon de-assertion of FRAME#)
Target retry
Target disconnect
Target abort
PI7C7100 handles these terminations in different ways, depending on the type of transaction being performed.
4.8.3.1 Delayed Write Target Termination Response
When PI7C7100 initiates a delayed write transaction, the type of target termination received from the target can be passed
back to the initiator. Table 4–7 shows the response to each type of target termination that occurs during a delayed write
transaction.
PI7C7100 repeats a delayed write transaction until one of the following conditions is met:
PI7C7100 completes at least one data transfer.
PI7C7100 receives a master abort.
PI7C7100 receives a target abort.
PI7C7100 makes 2
24
(default) or 2
32
(maximum) write attempts resulting in a response of target retry.
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參數(shù)描述
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