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418
Table 48
.
System Control Register Description (Continued)
BIT
SIGNAL
TYPE
FUNCTION
1
KEEPCLK
RW
Keep clock. When this bit is set, the PCI4510 device follows the CLKRUN protocol to maintain the
system PCLK and the CCLK (CardBus clock). This bit is global to the PCI4510 functions.
0 = Allow system PCLK and CCLK to stop (default)
1 = Never allow system PCLK or CCLK clock to stop
Note that the functionality of this bit has changed relative to that of the PCI12XX family of TI CardBus
controllers. In these CardBus controllers, setting this bit only maintains the PCI clock, not the CCLK.
In the PCI4510 device, setting this bit maintains both the PCI clock and the CCLK.
0
RIMUX
RW
PME/RI_OUT select bit. When this bit is 1, the PME signal is routed to the PME/RI_OUT terminal (PDV
21, GHK J03, RGVF T03). When this bit is 0 and bit 7 (RIENB) of the card control register is 1, the
RI_OUT signal is routed to the PME/RI_OUT terminal. If this bit is 0 and bit 7 (RIENB) of the card control
register is 0, then the output (21, J03, or T03) is placed in a high-impedance state. This terminal is
encoded as:
0 = RI_OUT signal is routed to the PME/RI_OUT terminal if bit 7 of the card control register is 1.
(default)
1 = PME signal is routed to the PME/RI_OUT terminal of the PCI4510 controller.
NOTE: If this bit (bit 0) is 0 and bit 7 of the card control register (PCI offset 91h, see Section 4.36) is
0, then the output on the PME/RI_OUT terminal is placed in a high-impedance state.
4.29 General Control Register
The general control register provides top level PCI arbitration control. It also provides the ability to disable the 1394
OHCI function and provides control over miscellaneous new functionality. See Table 49 for a complete description
of the register contents.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
General control
Type
R
R
R
R
R
RW
R
R
R
R
R
R
RW
R
RW
RW
Default
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
General control
86h
Read/Write, Read-only
0000h
Table 49. General Control Register Description
BIT
SIGNAL
TYPE
FUNCTION
1511
RSVD
R
Reserved. These bits return 0s when read.
10
12V_SW_SEL
RW
Power switch select. This bit selects which power switch is implemented in the system.
0 = The TPS2221 power switch is used (default).
1 = The TPS2211A power switch is used.
94
RSVD
R
Reserved. These bits return 0s when read.
3
DISABLE_OHCI
RW
When set, the open HCI 1394 controller function is completely nonaccessible and nonfunctional.
2
RSVD
R
Reserved. This bit returns 0 when read.
10
ARB_CTRL
RW
Controls top level PCI arbitration
00 = 1394 open HCI priority
01 = CardBus priority
10 = Fair round robin
11 = Fair round robin