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參數(shù)資料
| 型號(hào)： | PCI4510PDV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER |
| 中文描述： | PC卡和綜合1394A端口- 2000 OHCI的兩個(gè)端口物理層/鏈路層控制器 |
| 文件頁(yè)數(shù)： | 60/220頁(yè) |
| 文件大?。?/td> | 1356K |
| 代理商： | PCI4510PDV |
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316
PCI4510
PIC
MFUNC1
MFUNC2
MFUNC3
MFUNC4
MFUNC5
MFUNC6
IRQ3
IRQ4
IRQ5
IRQ10
IRQ11
IRQ15
Figure 312. IRQ Implementation
Power-on software is responsible for programming the multifunction routing status register to reflect the IRQ
configuration of a system implementing the PCI4510 device. The multifunction routing status register is shared
between the two PCI4510 functions, and only one write to function 0 or 1 is necessary to configure the
MFUNC6MFUNC0 signals. Writing to function 0 only is recommended. See Section 4.34,
Multifunction Routing
Status Register
,
for details on configuring the multifunction terminals.
The parallel ISA-type IRQ signaling from the MFUNC6MFUNC0 terminals is compatible with the input signal
requirements of the 8259 PIC. The parallel IRQ option is provided for system designs that require legacy ISA IRQs.
Design constraints may demand more MFUNC6MFUNC0 IRQ terminals than the PCI4510 device makes available.
3.7.4
Using Parallel PCI Interrupts
Parallel PCI interrupts are available when exclusively in parallel PCI interrupt/parallel ISA IRQ signaling mode, and
when only IRQs are serialized with the IRQSER protocol. Both INTA and INTB can be routed to MFUNC terminals
(MFUNC0 and MFUNC1). However, interrupts of both socket functions can be routed to INTA (MFUNC0) if bit 29
(INTRTIE) is set in the system control register (PCI offset 80h, see Section 4.28).
The INTRTIE bit affects the read-only value provided through accesses to the interrupt pin register (PCI offset 3Dh,
see Section 4.23). When the INTRTIE bit is set, both functions return a value of 01h on reads from the interrupt pin
register for both parallel and serial PCI interrupts. Table 39 summarizes the interrupt signaling modes.
Table 39. Interrupt Pin Register Cross Reference
INTRTIE BIT
INTPIN
FUNCTION 0
FUNCTION 1
0
01h
02h
1
01h
01h
3.7.5
Using Serialized IRQSER Interrupts
The serialized interrupt protocol implemented in the PCI4510 device uses a single terminal to communicate all
interrupt status information to the host controller. The protocol defines a serial packet consisting of a start cycle,
multiple interrupt indication cycles, and a stop cycle. All data in the packet is synchronous with the PCI clock. The
packet data describes 16 parallel ISA IRQ signals and the optional 4 PCI interrupts INTA, INTB, INTC, and INTD. For
details on the IRQSER protocol, refer to the document
Serialized IRQ Support for PCI Systems
.
3.7.6
SMI Support in the PCI4510 Device
The PCI4510 device provides a mechanism for interrupting the system when power changes have been made to the
PC Card socket interfaces. The interrupt mechanism is designed to fit into a system maintenance interrupt (SMI)
scheme. SMI interrupts are generated by the PCI4510 device, when enabled, after a write cycle to either the socket
control register (CB offset 10h, see Section 6.5) of the CardBus register set, or the ExCA power control register (ExCA
offset 02h/802h, see Section 5.3) causes a power cycle change sequence to be sent on the power switch interface.
The SMI control is programmed through three bits in the system control register (PCI offset 80h, see Section 4.28).
These bits are SMIROUTE (bit 26), SMISTATUS (bit 25), and SMIENB (bit 24). Table 310 describes the SMI control
bits function.
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| PCI4510RGVF | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Card & Integrated 1394a-2000 OHCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4510RZVF | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI Card & Integrated 1394a-2000 OHCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PCI4510ZHK | 制造商:Texas Instruments 功能描述: |
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| PCI4515 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
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