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參數(shù)資料
| 型號： | PCI4510PDV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER |
| 中文描述： | PC卡和綜合1394A端口- 2000 OHCI的兩個端口物理層/鏈路層控制器 |
| 文件頁數(shù)： | 66/220頁 |
| 文件大?。?/td> | 1356K |
| 代理商： | PCI4510PDV |
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PCI reset (PRST) has dual functionality based on whether PME is enabled or not. If PME is enabled,
then PME context is preserved. If PME is not enabled, then PRST acts the same as a normal PCI reset.
Please see the master list of PME context bits in Section 3.8.12.
Power source in D3
cold
if wake-up support is required from this state. Since V
CC
is removed in D3
cold
, an
auxiliary power source must be supplied to the PCI4510 V
CC
terminals. Consult the
PCI14xx
Implementation Guide for D3 Wake-Up
or the
PCI Power Management Interface Specification for PCI to
CardBus Bridges
for further information.
3.8.11 ACPI Support
The
Advanced Configuration and Power Interface (ACPI) Specification
provides a mechanism that allows unique
pieces of hardware to be described to the ACPI driver. The PCI4510 device offers a generic interface that is compliant
with ACPI design rules.
Two doublewords of general-purpose ACPI programming bits reside in PCI4510 PCI configuration space at offset
88h. The programming model is broken into status and control functions. In compliance with ACPI, the top level event
status and enable bits reside in the general-purpose event status register (PCI offset 88h, see Section 4.30) and
general-purpose event enable register (PCI offset 89h, see Section 4.31). The status and enable bits are
implemented as defined by ACPI and illustrated in Figure 315.
Event Output
Event Input
Enable Bit
Status Bit
Figure 315. Block Diagram of a Status/Enable Cell
The status and enable bits generate an event that allows the ACPI driver to call a control method associated with the
pending status bit. The control method can then control the hardware by manipulating the hardware control bits or
by investigating child status bits and calling their respective control methods. A hierarchical implementation would
be somewhat limiting, however, as upstream devices would have to remain in some level of power state to report
events.
For more information of ACPI, see the
Advanced Configuration and Power Interface (ACPI) Specification.
3.8.12 Master List of PME Context Bits and Global Reset-Only Bits for CardBus (Function 0)
If the PME enable bit (bit 8) of the power-management control/status register (PCI offset A4h, see Section 4.42) is
asserted, then the assertion of PRST does not clear the following PME context bits. If the PME enable bit is not
asserted, then the PME context bits are cleared with PRST. The PME context bits are:
Bridge control register (PCI offset 3Eh): bit 6
System control register (PCI offset 80h): bits 10, 9, 8
Power management CSR register (PCI offset A4h): bit 15, 8
ExCA power control register (ExCA offset 802h): bits 7, 5 (82365SL mode only), 43, 10
ExCA interrupt and general control register (ExCA offset 803h): bits 65
ExCA card status change register (ExCA offset 804h): bits 30
ExCA card status change interrupt configuration register (ExCA offset 805h): bits 30
CardBus socket event register (CardBus offset 00h): bits 30
CardBus socket mask register (CardBus offset 04h): bits 30
CardBus socket present state register (CardBus offset 08h): bits 27, 137, 51
CardBus socket control register (CardBus offset 10h): bits 64, 20
Global reset places all registers in their default state regardless of the state of the PME enable bit. The GRST signal
is gated only by the SUSPEND signal. This means that assertion of SUSPEND blocks the GRST signal internally,
thus preserving all register contents. The registers cleared only by GRST are:
Status register (PCI offset 06h): bits 1511, 8
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相關(guān)代理商/技術(shù)參數(shù) |
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| PCI4510RGVF | 功能描述:外圍驅(qū)動器與原件 - PCI Card & Integrated 1394a-2000 OHCI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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| PCI4515 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:SINGLE SOCKET CARDBUS CONTROLLER WITH INTEGRATED |
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