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| 型號： | PCI4510PDV |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PC CARD AND INTEGRATED 1394A-2000 OHCI TWO PORT PHY/LINK LAYER CONTROLLER |
| 中文描述： | PC卡和綜合1394A端口- 2000 OHCI的兩個端口物理層/鏈路層控制器 |
| 文件頁數(shù)： | 104/220頁 |
| 文件大小： | 1356K |
| 代理商： | PCI4510PDV |
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432
4.47 Serial Bus Control and Status Register
The serial bus control and status register communicates serial bus status information and selects the quick command
protocol. Bit 5 (REQBUSY) in this register must be polled during serial bus byte reads to indicate when data is valid
in the serial bus data register. See Table 425 for a complete description of the register contents.
Bit
7
6
5
4
3
2
1
0
Name
Serial bus control and status
Type
RW
R
R
R
RW
RW
RC
RC
Default
0
0
0
0
0
0
0
0
Register:
Offset:
Type:
Default:
Serial bus control and status
B3h (Function 0)
Read-only, Read/Write, Read/Clear
00h
Table 425. Serial Bus Control and Status Register Description
BIT
SIGNAL
TYPE
FUNCTION
7
PROT_SEL
RW
Protocol select. When bit 7 is set, the send-byte protocol is used on write requests and the receive-byte
protocol is used on read commands. The word address byte in the serial bus index register (see
Section 4.45) is not output by the PCI4510 device when bit 7 is set.
6
RSVD
R
Reserved. Bit 6 returns 0 when read.
5
REQBUSY
R
Requested serial bus access busy. Bit 5 indicates that a requested serial bus access (byte read or write)
is in progress. A request is made, and bit 5 is set, by writing to the serial bus slave address register (see
Section 4.46). Bit 5 must be polled on reads from the serial interface. After the byte read access has been
requested, the read data is valid in the serial bus data register.
4
ROMBUSY
R
Serial ROM busy status. Bit 4 indicates the status of the PCI4510 serial ROM circuitry. Bit 4 is set during
the loading of the subsystem ID and other default values from the serial bus ROM.
0 = Serial ROM circuitry is not busy
1 = Serial ROM circuitry is busy
3
SBDETECT
RW
Serial bus detect. When bit 3 is set, it indicates that the serial bus interface is detected through a pullup
resistor on the SCL terminal after reset.
0 = Serial bus interface not detected
1 = Serial bus interface detected
2
SBTEST
RW
Serial bus test. When bit 2 is set, the serial bus clock frequency is increased for test purposes.
0 = Serial bus clock at normal operating frequency,
1 = Serial bus clock frequency increased for test purposes
100 kHz (default)
1
REQ_ERR
RC
Requested serial bus access error. Bit 1 indicates when a data error occurs on the serial interface during
a requested cycle and may be set due to a missing acknowledge. Bit 1 is cleared by a writeback of 1.
0 = No error detected during user requested byte read or write cycle
1 = Data error detected during user requested byte read or write cycle
0
ROM_ERR
RC
ROM data error status. Bit 0 indicates when a data error occurs on the serial interface during the auto-load
from the serial bus ROM and may be set due to a missing acknowledge. Bit 0 is also set on invalid ROM
data formats. See Section 3.6.3,
Serial Bus EEPROM Application
, for details on ROM data format. Bit 0 is
cleared by a writeback of 1.
0 = No error detected during auto-load from serial bus ROM
1 = Data error detected during auto-load from serial bus ROM
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