1999 May 03
6
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
7
PINNING
SYMBOL
PIN
DESCRIPTION
NR. TYPE
(1)
ACTIVE
LEVEL
ACTIVE
EDGE
rising
I
DD
ADO
ADI
AFS
1
2
3
O/TS
I
I
1.5 mA
audio digital interface PCM data output to DSP
audio digital interface PCM data input from DSP
audio digital interface PCM frame synchronization signal
from DSP
audio digital interface PCM clock signal from DSP
asynchronous reset input
low-swing master clock input; f
clk
= 13 MHz; integrated
capacitive coupling
digital power supply
digital ground
control bus clock input from DSP
control bus data enable from DSP
control bus data input from DSP
control bus data output to DSP
status control signal for activation of AUXDAC1,
AUXDAC2 and MCLK input
general purpose output pin
baseband interface data clock
baseband transmit interface data enable signal
baseband interface data I/O from/to DSP
baseband receive interface data enable signal
baseband transmit path activation signal
baseband receive path activation signal
(I) baseband differential positive input/output to IF circuit
(I) baseband differential negative input/output to
IF circuit
(Q) baseband differential positive input/output to
IF circuit
(Q) baseband differential negative input/output to
IF circuit
baseband power supply (analog)
baseband ground (analog)
auxiliary ADC input 1 for battery voltage measurement
auxiliary ADC input 2
auxiliary ADC input 3
auxiliary ADC input 4
auxiliary DAC output for AGC; max. load 50 pF // 2 k
auxiliary DAC output for AFC; max. load 50 pF // 10 k
ACLK
RESET
MCLK
4
5
6
I
I
I
rising
rising
LOW
V
DDD
V
SSD
CCLK
CEN
CDI
CDO
AUXST
7
8
9
10
11
12
13
P
G
I
I
I
falling
LOW
HIGH
O/TS
I
1.5 mA
AMPCTRL
BIOCLK
BIEN
BDIO
BOEN
TXON
RXON
IP
IN
14
15
16
17
18
19
20
21
22
O
1.5 mA
3 mA
1.5 mA
1.5 mA
1.5 mA
O/TS
O
I/O
O
I
I
I/O
I/O
LOW
LOW
HIGH
HIGH
QP
23
I/O
QN
24
I/O
V
DDA(bb)
V
SSA(bb)
AUXADC1
AUXADC2
AUXADC3
AUXADC4
AUXDAC1
AUXDAC2
25
26
27
28
29
30
31
32
P
G
I
I
I
I
O
O