參數(shù)資料
型號(hào)： PCF50732
廠商： NXP Semiconductors N.V.
英文描述： Baseband and audio interface for GSM
中文描述： 用于GSM基帶和音頻接口
文件頁(yè)數(shù)： 56/64頁(yè)
文件大?。?/td> 322K
代理商： PCF50732
1999 May 03
56
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
19.1
Wake-up procedure from Sleep mode
Apart from being the status control signal of AUXDAC1,
AUXDAC2 and the MCLK input, AUXST also starts a
down-counter at each rising edge which controls the
output drive capability of pin V
ref
. This is important for the
following considerations. For current consumption
reduction during Sleep mode there are
two
possibilities as
shown in Section 19.1.1 and 19.1.2.
19.1.1
P
OSSIBILITY
1
Program every block into power-down via CSI except for
the band gap, then pull AUXST LOW to switch off the clock
internally. This results in a I
DD(total)
= 60
μ
A (typical). Since
the band gap hasn’t been programmed into power-down,
the only active reference is V
ref
. After a rising edge of
AUXST, POST
DAC
is in the order of 1.5 ms.
19.1.2
P
OSSIBILITY
2
If AUXST is also used to switch off the analog power
supply, all references are shut down. The power-up time in
this case is measured from the point where the MCLK
clock input has valid levels or V
DDA
has settled to its final
value (the latter of the two signals sets the reference
point).
A down-counter increases the band gap output drive
capability for 32768 MCLK cycles which equals
approximately 2.5 ms. After that time the voltage at V
ref
has reached
±
0.5 mV of its final value. The timing diagram
illustrates the situation (see Fig.15). Other points to note
for this possibility:
As long as V
DDD
is not switched off, all registers keep
their values.
As long as V
DDA(bb)
is not stable, the internal master
clock is not running, because the first stage of the clock
generator is supplied by V
DDA.
All digital signals
MUST
remain stable for t
MCLK
after
AUXST has gone HIGH. This is necessary to avoid any
timing violations in the digital part of the PCF50732
caused by an unstable MCLK clock input.
The previously mentioned 2.5 ms for t
BG
are only valid
for
C
Vref
= 68 nF
±
10%
or less. The maximum of value
68 nF is highly recommended for good noise and power
supply rejection figures.
Fig.15 Possible timing of wake-up sequence.
handbook, full pagewidth
MGR999
tVDD
tBG
(2.5 ms)
tMCLK
POSTDAC
(4 ms)
VDDA
Vref
AUXST
MCLK
AUXDAC1/
AUXDAC2
t
VDD
: settling time until V
DDA(bb)
has reached 95% of its final value. It is assumed that t
MCLK
> t
VDD
; otherwise t
BG
and POST
DAC
are related to t
VDD
.
t
MCLK
: settling time until MCLK clock has reached at least 100 mV (peak-to-peak) level and a frequency of 13 MHz
±
10 kHz.
t
BG
: settling time until voltage at V
ref
has reached
±
0.5 mV of its final value for
C
Vref
= 68 nF
±
10%.
POST
DAC
: settling time until AUXDAC1 and AUXDAC2 has reached the previously programmed value
±
2 LSBs.
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