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參數(shù)資料
| 型號： | PCF50732 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | 用于GSM基帶和音頻接口 |
| 文件頁數(shù)： | 21/64頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PCF50732 |
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1999 May 03
21
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
11 AUXILIARY FUNCTIONS
The auxiliary functions part consists of three
digital-to-analog converters (DACs) and a 4 input
analog-to-digital converter (ADC) with a 12-bit range.
The DACs are for:
Automatic Gain Control (AGC): AUXDAC1
Automatic Frequency Control (AFC): AUXDAC2
Power ramping: AUXDAC3.
11.1
Automatic Gain Control (AGC): AUXDAC1
The AUXDAC1 is an 8-bit binary coded, guaranteed
monotonic digital-to-analog converter.
The status of AUXDAC1 is controlled by the signal AUXST
and a power-up bit in the Power control register. The signal
that switches the external VCXO can also be used to
control the AUXST pin of the PCF50732. The AUXDAC1
output is floating in Power-down mode (AUXST = LOW).
The input MCLK is then deactivated.
When AUXST goes HIGH, AUXDAC1 is powered-up and
the converted value of the corresponding register in the
control register block is available at the AUXDAC1 output
pin.
If a write access to the AUXDAC1 register occurs, the DAC
is activated with the new content of the DAC register (see
Table 14 and 15). The AUXDAC1 must be powered-up by
setting the correct bit in the Power control register. At reset
AUXDAC1 is powered-down.
11.2
Automatic Frequency Control (AFC):
AUXDAC2
The AUXDAC2 is a 12-bit binary coded, guaranteed
monotonic digital-to-analog converter. This DAC is used to
control the frequency of an external master clock VCXO.
The status of AUXDAC2 is controlled by the signal AUXST
and a power-up bit in the Power control register. The signal
that switches the external VCXO can also be used to
control the AUXST pin of the PCF50732. The AUXDAC2
output is floating in Power-down mode (AUXST = LOW).
When AUXST goes HIGH, AUXDAC2 is powered-up and
the converted value of the corresponding register in the
control register block is available at the AUXDAC2 output
pin.
The default value for AUXDAC2 is 1.1 V which
corresponds to a 800H code in the AUXDAC2 register.
At reset AUXDAC2 is powered on.
11.3
Power ramping: AUXDAC3
AUXDAC3 is a 10-bit binary coded digital-to-analog
converter designed for power ramping purposes.
AUXDAC3 is default off. The power ramping behaviour is
described in Section 9.3.2.2.
11.4
Auxiliary analog-to-digital converter (AUXADC)
The AUXADC is specified for voltage and temperature
measurements. It contains 4 input channels required for
T and
V measurements, as well as battery type
recognition:
T: battery temperature, ambient temperature
(measured across sensor)
V: peak battery voltage, battery voltage during transmit
burst.
Five 12-bit registers are available in which results of
auxiliary analog-to-digital conversions can be stored.
Two registers are dedicated to the input AUXADC1 and
one to each of AUXADC2, AUXADC3 and AUXADC4.
The AUXADC1 input can be used for battery voltage
measurement. In the AUXADC1A register the voltage
during a transmit time slot can be stored. The AUXADC1B
register can store the voltage during other time slots. If a
read request to one of these registers is executed by
loading its address into the Read request register, the
actual contents of the addressed register are given to the
control interface and a new measurement is performed in
the next appropriate time slot.
A multiplexer connects each of the AUXADC inputs to a
channel of the receive ADC depending on read access to
the corresponding register.
Thus an auxiliary analog-to-digital conversion is only
possible, if the baseband receive section is not in use
(RXON is LOW). At each read request to one of the
AUXADC registers, a flag is set in the AUXADC flag
register indicating that an analog-to-digital conversion is to
be performed. When one of the registers AUXADC1B,
AUXADC2, AUXADC3, or AUXADC4 is being read, the
baseband interface verifies that RXON is LOW, indicating
that no receive burst is currently active. The baseband
receive path is then powered up. After the ADC settling
time has elapsed (see POST
AUXADC
in Chapter 18), valid
data is available and stored in the corresponding register.
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