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參數資料
| 型號： | PCF50732 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Baseband and audio interface for GSM |
| 中文描述： | 用于GSM基帶和音頻接口 |
| 文件頁數： | 28/64頁 |
| 文件大?。?/td> | 322K |
| 代理商： | PCF50732 |
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1999 May 03
28
Philips Semiconductors
Objective specification
Baseband and audio interface for GSM
PCF50732
Table 19
AUXADC control registers value description
12.3.5
AUXADC
REGISTERS
Table 20
AUXADC registers overview
Table 21
AUXADC registers value description
VALUE OF
DESCRIPTION
AUXADC conversion delay
value register
The 7-bit value (b6 to b0) denotes the delay measured in 48MCLK units between the
rising edge of TXON and the conversion on AUXADC1A. The normal power-on
settling time is added to this delay. Default value is 0.
The AUXADC flag register returns the status of the AUXADC converters. If an
auxiliary A/D conversion is pending, the flag of the corresponding AUXADC will be
set. The flag register is read only.
The offset value registers contain signed 9-bit offset compensation values. These
values are subtracted automatically from all baseband receive (BBRX) and AUXADC
measurements to compensate for offset errors. The compensation values can be
read and written and have a default value of 0. It can also be measured by the device
itself.
AUXADC flag register
AUXADC offset value register
I channel offset value register
Q channel offset value register
Offset trigger register
A write to the Offset trigger register will trigger an offset measurement for each of the
channels (Q-off, I-off or AUXADC) selected.
Offset measurements are special cases of AUXADC measurements and are done
sequentially. Each calibration measurement takes approximately 100
μ
s. The Offset
trigger register is write only.
ADDR.
REGISTER NAME
VALUE
11
10
9
8
7
6
5
4
3
2
1
0
0101
0110
0111
1000
1001
AUXADC channel 1 register A (AUXADC1A)
AUXADC channel 1 register B (AUXADC1B)
AUXADC channel 2 register (AUXADC2)
AUXADC channel 3 register (AUXADC3)
AUXADC channel 4 register (AUXADC4)
b11 b10
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
VALUE OF
DESCRIPTION
AUXADC1A 12-bit result of the A/D conversion on AUXADC channel 1, measured during a transmission burst
AUXADC1B 12-bit result of the A/D conversion on AUXADC channel 1, measured outside a transmission burst
AUXADC2
12-bit result of the A/D conversion on AUXADC channel 2
AUXADC3
12-bit result of the A/D conversion on AUXADC channel 3
AUXADC4
12-bit result of the A/D conversion on AUXADC channel 4
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