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參數(shù)資料
| 型號： | PCA9541 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 2-to-1 I2C master selector with interrupt logic and reset |
| 中文描述： | 2比1的I2C主機選擇與中斷邏輯和復位 |
| 文件頁數(shù)： | 23/30頁 |
| 文件大小： | 279K |
| 代理商： | PCA9541 |
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Philips Semiconductors
Product data sheet
PCA9541
2-to-1 I
2
C demultiplexer with interrupt logic and reset
2004 Oct 01
22
AC CHARACTERISTICS
SYMBOL
PARAMETER
STANDARD-MODE
I
2
C-bus
MIN
—
0
50
4.7
FAST-MODE
I
2
C-bus
MIN
—
0
50
1.3
UNIT
MAX
0.3
1
100
150
—
MAX
0.3
1
400
150
—
t
pd
f
SCL
f
SCLIR
t
BUF
Propagation delay from SDA to SD
n
or SCL to SC
n
SCL clock frequency
SCL bus initialization/recovery clock frequency
Bus free time between a STOP and START condition
Hold time (repeated) START condition
After this period, the first clock pulse is generated
LOW period of the SCL clock
HIGH period of the SCL clock
Set-up time for a repeated START condition
Set-up time for STOP condition
Data hold time
Data set-up time
Rise time of both SDA and SCL signals
Fall time of both SDA and SCL signals
Capacitive load for each bus line
Pulse width of spikes which must be suppressed
by the input filter
Data valid (HL)
4
Data valid (LH)
4
Data valid Acknowledge
INT0 and INT1 outputs
t
iv
INT_in to INT1 or INT2 active valid time
t
ir
INT_in to IINT1 or INT2 inactive delay time
L
pwr
LOW level pulse width rejection or INT_in input
H
pwr
HIGH level pulse width rejection or INT_in input
RESET
t
W
Pulse width LOW reset
t
rst
Reset time (SDA clear)
t
REC:STA
Recovery to Start
5, 6
NOTES:
1. Pass gate propagation delay is calculated from the 20
typical R
ON
and the 15 pF load capacitance.
2. A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the V
IH(min)
of the SCL signal) in order to bridge
the undefined region of the falling edge of SCL.
3. C
b
= total capacitance of one bus line in pF.
4. Measurements taken with 1 k
pull-up resistor and 50 pF load.
5. Resetting the device while actively communicating on the bus may cause glitches or errant STOP conditions.
6. Upon reset, the full delay will be the sum of t
RESET
and the RC time constant of the SDA bus.
ns
kHz
kHz
μ
s
t
HD;STA
4.0
—
0.6
—
μ
s
t
LOW
t
HIGH
t
SU;STA
t
SU;STO
t
HD;DAT
t
SU;DAT
t
R
t
F
C
b
4.7
4.0
4.7
4.0
0
2
250
—
—
—
—
—
—
—
3.45
—
1000
300
400
1.3
0.6
0.6
0.6
0
2
100
—
—
—
—
0.9
—
300
300
400
μ
s
μ
s
μ
s
μ
s
μ
s
ns
ns
μ
s
μ
s
20 + 0.1C
b3
20 + 0.1C
b3
—
t
SP
—
50
—
50
ns
t
VD:DATL
t
VD:DATH
t
VD:ACK
—
—
—
1
—
—
—
1
μ
s
μ
s
μ
s
0.6
1
0.6
1
—
—
1
0.5
4
2
—
—
—
—
1
0.5
4
2
—
—
μ
s
μ
s
ns
μ
s
4
—
—
—
4
—
—
—
ns
ns
ns
500
0
500
0
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCA9541_08 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
| PCA9541_09 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
| PCA9541A | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
| PCA9541ABS/01 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset |
| PCA9541ABS/01,118 | 功能描述:I2C 接口集成電路 2-to-1 I2C-bus master selector RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16 |
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