參數(shù)資料
型號： PCA9541
廠商： NXP Semiconductors N.V.
英文描述： 2-to-1 I2C master selector with interrupt logic and reset
中文描述： 2比1的I2C主機(jī)選擇與中斷邏輯和復(fù)位
文件頁數(shù)： 2/30頁
文件大小： 279K
代理商： PCA9541
Philips Semiconductors
Product data sheet
PCA9541
2-to-1 I
2
C master selector with interrupt logic and reset
2
2004 Oct 01
FEATURES
2-to-1 bi-directional master selector
I
2
C interface logic; compatible with SMBus standards
PCA9541/01 powers-up with Channel 0 selected
PCA9541/02 powers-up with Channel 0 selected after STOP
condition detected (bus idle) on Channel 0
PCA9541/03 powers-up with no channel selected and either
master can take control of the bus
Active LOW Interrupt Input
2 Active LOW Interrupt Outputs
Active LOW Reset Input
4 address pins allowing up to 16 devices on the I
2
C-bus
Channel selection via I
2
C-bus
Bus initialization/recovery function
Bus traffic sensor
Low Rds
ON
switches
Allows voltage level translation between 1.8 V, 2.5 V, 3.3 V and
5 V buses
No glitch on power-up
Supports hot insertion
Software identical for both masters
Low stand-by current
Operating power supply voltage range of 2.3 V to 5.5 V
6.0 V tolerant Inputs
0 to 400 kHz clock frequency
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Packages offered: SO16, TSSOP16, HVQFN16
APPLICATIONS
High reliability systems with dual masters
Gatekeeper multiplexer on long single bus
Bus initialization/recovery for slave devices without hardware
reset
Allows masters without arbitration logic to share resources
DESCRIPTION
The PCA9541 is a 2-to-1 I
2
C master selector designed for high
reliability dual master I
2
C applications where system operation is
required, even when one master fails or the controller card is
removed for maintenance. The two masters (e.g., primary and
back-up) are located on separate I
2
C-buses that connect to the
same downstream I
2
C-bus slave devices. I
2
C commands are sent
by either I
2
C-bus master and are used to select one master at a
time. Either master at any time can gain control of the slave devices
if the other master is disabled or removed from the system. The
failed master is isolated from the system and will not affect
communication between the on-line master and the slave devices on
the downstream I
2
C-bus.
Three versions are offered for different architectures. PCA9541/01
with channel 0 selected at start-up, PCA9541/02 with channel 0
selected after start-up and after stop condition is detected, and
PCA9541/03 with no channel selected after start-up.
The interrupt outputs are used to provide an indication of which
master has control of the bus. One interrupt input (INT_IN) collects
downstream information and propagates it to the 2 upstream
I
2
C-buses (INT0 and INT1) if enabled. INT0 and INT1 are also used
to let the previous bus master know that it is not in control of the bus
anymore and to indicate the completion of the bus
recovery/initialization sequence. Those interrupts can be disabled
and will not generate an interrupt if the masking option is set.
A bus recovery/initialization if enabled sends nine clock pulses, a
not acknowledge, and a stop condition in order to set the
downstream I
2
C-bus devices to an initialized state before actually
switching the channel to the selected master.
An interrupt is sent to the upstream channel when the
recovery/initialization procedure is completed.
An internal bus sensor senses the downstream I
2
C traffic and
generates an interrupt if a channel switch occurs during a non-idle
bus condition. This function is enabled when the PCA9541
recovery/initialization is not used. The interrupt signal informs the
master that an external I
2
C-bus recovery/initialization needs to be
performed. It can be disabled and an interrupt will not be generated.
The pass gates of the switches are constructed such that the V
DD
pin can be used to limit the maximum high voltage, which will be
passed by the PCA9541. This allows the use of different bus
voltages on each pair, so that 1.8 V 2.5 V or 3.3 V devices can
communicate with 5 V devices without any additional protection.
The PCA9541 does not isolate the capacitive loading on either side
of the device so the designer must take into account all trace and
device capacitances on both sides of the device, and pull-up
resistors must be used on all channels.
External pull-up resistors pull the bus to the desired voltage level for
each channel. All I/O pins are 6.0 V tolerant.
An active-LOW Reset Input allows the PCA9541 to be initialized.
Pulling the RESET pin LOW resets the I
2
C state machine and
configures the device to its default state as does the internal power
on reset function.
相關(guān)PDF資料
PDF描述
PCA9542 2-channel IIC multiplexer and interrupt controller(2通道IIC多路復(fù)用器和中斷控制器)
PCA9542PW 2-channel I2C multiplexer and interrupt controller
PCA9542PWDH 2-channel I2C multiplexer and interrupt controller
PCA9543 2-channel I2C switch with interrupt logic and reset
PCA9543D 2-channel I2C switch with interrupt logic and reset
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PCA9541_08 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541_09 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541A 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541ABS/01 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:2-to-1 I2C-bus master selector with interrupt logic and reset
PCA9541ABS/01,118 功能描述:I2C 接口集成電路 2-to-1 I2C-bus master selector RoHS:否 制造商:NXP Semiconductors 電源電壓-最大:5.5 V 電源電壓-最小:2.3 V 最大工作頻率:400 KHz 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-16
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