參數(shù)資料
型號(hào)： PC34704BEP
廠(chǎng)商： FREESCALE SEMICONDUCTOR INC
元件分類(lèi)： 電源管理
英文描述： 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC56
封裝： 7 X 7 MM, 1 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-56
文件頁(yè)數(shù)： 30/50頁(yè)
文件大小： 2010K
代理商： PC34704BEP
Analog Integrated Circuit Device Data
36
Freescale Semiconductor
34704
FUNCTIONAL DEVICE OPERATION
COMPONENT CALCULATION
COMPONENT CALCULATION
FSW1 AND GENERAL SOFT START
CONFIGURATION
The 34704 uses FSW1 as the switching frequency for
REG1(VG) thru REG5, and this can be changed by applying
a voltage between 0 to 2.5V to the FREQ pin. If the FREQ pin
is left unconnected, the 34704 starts up with a default
frequency of 750KHz. To configure the FSW1, use a 2
resistors voltage divider from VDDI to ground to set the
voltage on the FREQ pin as indicated bellow:
1.
If an external voltage is used, FSW1 can only be set during
device startup.
Initially at power up, the soft start time will be set for all of
the regulators through programming the SS pin with an
external resistor divider connected between VDDI and AGND
as follows:
REGULATORS POWER STAGE AND
COMPENSATION CALCULATION
Regulator 1 and 6 (Synchronous Boost - internally
compensated - REG1 is VG supply).
REG1 is a Synchronous Boost converter set to 5V and
Maximum current of 500mA while REG6 is set to 15V at
60ma(on the 34704B, REG1 does not exist but similar
circuitry is used to provide the internal VG voltage). They do
not need an external compensation network, thus, the only
components that need to be calculated are:
L: A boost power stage can be designed to operate in
CCM for load currents above a certain level usually 5 to
15% of full load. The minimum value of inductor to
maintain CCM can be determined by using the following
procedure:
1. Define IOB as the minimum current to maintain CCM as
15% of full load.
2. However the worst case condition for the boost power
stage is when the input voltage is equal to one half of
the output voltage, which results in the Maximum
I
L,
then:
Note: On the 34704B Use the recommended 3.0uH
inductor rated between 50 to 100mA in order to have this
regulator working in DCM. Rising the inductor value will make
the regulator to begin working in CCM.
COUT: The three elements of output capacitor that
contribute to its impedance and output voltage ripple are
the ESR, the ESL and the capacitance C. The minimum
capacitor value is approximately:
Where
VO
r is the desired output voltage ripple.
Ratio
FSW1
[KHz]
0
750
9/32
1000
13/32
1250
17/32
1500
21/32
1750
VDDI
2000
Ratio
Soft Start timing
[ms]
0
0.5
11/32
2.0
19/32
8.0
VDDI
32.0
IDD max = 100Α
VDDI
GND
FREQ
RF1
RF2
VFREQ
VDDI
RF2
RF1 RF2
+
----------------------------
=
VFREQ
RF1, RF2 tolerance
±1.0%
VDDI
GND
SS
RSS1
RSS2
VSS
VDDI
RSS2
RSS1 RSS2
+
-----------------------------------
=
VSS
RSS1, RSS2 tolerance
±1.0%
[H]
OB
I
T
D
Vo
L
2
)
1
)(
(
2
min
≥
OB
I
T
Vo
L
16
)
(
min ≥
[H]
r
OUT
Vo
Fsw
D
Io
C
≥
max
[F]
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