參數(shù)資料
型號： PC34704BEP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 電源管理
英文描述： 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC56
封裝： 7 X 7 MM, 1 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-56
文件頁數(shù)： 24/50頁
文件大?。?/td> 2010K
代理商： PC34704BEP
Analog Integrated Circuit Device Data
30
Freescale Semiconductor
34704
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
LOGIC COMMANDS AND REGISTERS
I2C USER INTERFACE
The 34704 communicates via I2C using a default device
address $54 to access all user registers and program all
regulators features independently.
USER PROGRAMMABLE REGISTERS
GrpC/E power sequencing setting (34704A Only)
The microprocessor can choose one of several voltage
sequence options for the GrpC/E supply (REG5), high
voltage supply (REG6), and negative voltage supply (REG7).
For 3 of the sequencing options, REG5 supply is controlled
and tied with REG6 and REG7 in a preset power sequence.
For one sequencing option, only REG6 and REG7 are
involved in the power sequence and REG5 is independent.
34704A assigns a 2-bit register to program the GrpC/E
power sequencing options (CCDSEQ Register). This register
value is latched in at GrpC power up and will not be allowed
to change unless a power recycle happens.
Switching frequency for REG6, 7 & 8
FSW2 can be selected to be between 250kHz and 1.0MHz
in 250kHz steps. On the 34704B, FSW2 is just for REG8
since REG6 and 7 do not exist in this device.
34704 assigns a 2-bit register to program FSW2 (FSW2
Register)
Shutdown Hold (Delay) Time
The 34704 assigns a 2-bit register (SDDELAY Register)
for the processor to program the shutdown delay time period
Please refer to the /ONOFF pin description for more
details
Programming 34704 response to under-voltage/over-
voltage conditions on each regulator
There are two responses that can be programmed for an
overvoltage/undervoltage condition:
Response A: When an overvoltage (undervoltage) event is
detected, the concerned output shuts down and a register is
flagged to alert the processor.
Response B: When an overvoltage/undervoltage event is
detected, the concerned output will not shutdown, but the
register is flagged to alert the processor. Then, the processor
can decide whether to shutdown the output or not. In the
mean time, the concerned output control loop will be
attempting to correct the error.
page 29 for more details.
Response A and Response B share the same flag register
34704 assigns a 1-bit register for this function
(OVUVSETx Register) where x corresponds to each
regulator
OPTION
MSB
LSB
GRPC/E ENABLED
GRPC/E DISABLED
1
(Default)
0
REG5 is independently controlled
REG6 and REG7 ramp up together.
REG5 is independently controlled
REG6 and REG7 ramp down together
2
0
1
REG5 ramps up first
Then REG6 and REG7 ramp up together
REG5, REG6 and REG7 ramp down together
3
1
0
REG5, REG6, and REG7 ramp up together
REG5, REG6, and REG7 ramp down together
4
1
REG5 and REG6 ramp up together first.
Then ramp up REG7
REG7 ramps down first.
Then REG5 and REG6 ramp down together
FSW2
MSB
LSB
500kHz (Default)
0
250kHz
0
1
750kHz
1
0
1000kHz
1
Shutdown Delay
MSB
LSB
1.0sec (Default)
0
0.5sec
0
1
1.5sec
1
0
2.0sec
1
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