參數(shù)資料
型號(hào)： PC34704BEP
廠商： FREESCALE SEMICONDUCTOR INC
元件分類： 電源管理
英文描述： 8-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC56
封裝： 7 X 7 MM, 1 MM HEIGHT, 0.40 MM PITCH, ROHS COMPLIANT, QFN-56
文件頁(yè)數(shù)： 21/50頁(yè)
文件大小： 2010K
代理商： PC34704BEP
Analog Integrated Circuit Device Data
28
Freescale Semiconductor
34704
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
In any of the previous shutdown sequences, VG output will
stay alive to maintain internal circuitry and logic until all
other regulators are off, then it will shut off.
POWER SUPPLY
The battery voltage range is the following depending on
the application:
1-cell Li-Ion/Polymer: 2.7V to 4.2V. Typ value is 3.6V
USB supply or AC wall adapter: 4.5V to 5.5V. Typ value is
5.0V. This gives a total input voltage supply range of 2.7V
to 5.5V
For the regulators, each one will be supplied separately
through its own power input.
LION PIN
LION pin is always tied to VIN level.
FREQUENCY SETTING PIN (FREQ PIN)
There are two switching frequencies on board the 34704,
one for REG6, 7 & 8, and the other for the rest of the
regulators. To avoid any jitter or interference problems by
having two oscillators on board, the switching frequency will
be derived from the main oscillator using a frequency divider.
The switching frequency will be selectable for all of the
regulators. REG6, 7 & 8 switching frequency (FSW2) will be
selectable through I2C to be between 250 kHz and 1.0 MHz
in 250 kHz steps. The rest of the regulators switching
frequency (FSW1) will be selectable through the FREQ pin
and can be selected between 750 kHz and 2.0 MHz, in 250
kHz steps.
FSW1 default value is 2.0MHz. This value is obtained by
tying the FREQ pin to VDDI. FSW2 default value is 500 kHz
FSW1 will be selectable through programming the FREQ
pin with an external resistor divider connected between VDDI
and AGND pins. FSW2 will only be selectable through I2C.
Please refer to the “I2C Programmability” section.
The 34704 uses 4 different phases of switching (clock is
80 degrees out of phase) for FSW1 to spread out the current
draw by the individual converters from the input supply over
time to reduce the peak input current demand. This allows for
better EMI performance and reduction in the input filter
requirements. FSW1 has no phase relation with FSW2. The
following distribution is shown for FSW1 of 2.0MHz. The
regulators grouping is based on their maximum current draw
and attempts to reduce the effect on the input current draw.
SOFT START PIN (SS PIN)
Initially at power up, the soft start time will be set for all of
the regulators through programming the SS pin with an
external resistor divider connected between VDDI and AGND
After power up, the soft start value for REG5 through
REG8 can be changed and programmed through I2C. REG2
through REG4 soft start value is only set by the SS pin and
cannot be programmed through I2C.
See section “I2C Programmability” for more details.
ONOFF PIN
This is a hardware enable/disable feature OR pin for
the 34704:
It can be connected to a mechanical switch to turn the
power On or Off
The device is power off by a command via the I2C interface
as well
The power off by hardware can be masked by a command
via the I2C interface
If the device is off and a falling edge is detected at the
ONOFF pin, the device starts up
If and only if the device is on and the ONOFF pin is pulled
down for a time period (1s as a default and selectable to
2.0sec, 1.5sec, 1.0sec or 0.5sec via the I2C interface),
then the device powers off after a second time period
elapses unless it is masked by a command via the I2C
interface:
The second period is the same amount of time as the
first period so that the counter can be shared
When the first period elapses a shutdown flag is set to
alert the processor that a shutdown signal has been
activated. The ONOFF pin can be released after this
flag is set without affecting what will happen next
A CPU can read out the shutdown flag to determine
what to do
Power off the device immediately by a command via I2C
interface (ALLOFF command)
Ignore the power off by sending a command via I2C
interface to clear the shutdown flag
Do nothing until the second time period expires and let
the device power off by itself
The ONOFF pin is edge sensitive and activates on a falling
edge. It is normally pulled high.
500ns
REG1/VG
REG2
REG5, REG3
REG4
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