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參數(shù)資料
| 型號(hào)： | PC28F640J3C-120 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲(chǔ)器（J3） |
| 文件頁數(shù)： | 68/72頁 |
| 文件大?。?/td> | 905K |
| 代理商： | PC28F640J3C-120 |
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256-Mbit J3 (x8/x16)
68
Datasheet
Appendix C Design Considerations
C.1
Three-Line Output Control
The device will often be used in large memory arrays. Intel provides five control inputs (CE0, CE1,
CE2, OE#, and RP#) to accommodate multiple memory connections. This control provides for:
a.
Lowest possible memory power dissipation.
b.
Complete assurance that data bus contention will not occur.
To use these control inputs efficiently, an address decoder should enable the device (see
Table 13
)
while OE# should be connected to all memory devices and the system’s READ# control line. This
assures that only selected memory devices have active outputs while de-selected memory devices
are in standby mode. RP# should be connected to the system POWERGOOD signal to prevent
unintended writes during system power transitions. POWERGOOD should also toggle during
system reset.
C.2
STS and Block Erase, Program, and Lock-Bit Configuration
Polling
STS is an open drain output that should be connected to VCCQ by a pull-up resistor to provide a
hardware method of detecting block erase, program, and lock-bit configuration completion. It is
recommended that a 2.5k resister be used between STS# and VCCQ. In default mode, it transitions
low after block erase, program, or lock-bit configuration commands and returns to High Z when
the WSM has finished executing the internal algorithm. For alternate configurations of the STS
signal, see the Configuration command.
STS can be connected to an interrupt input of the system CPU or controller. It is active at all times.
STS, in default mode, is also High Z when the device is in block erase suspend (with programming
inactive), program suspend, or in reset/power-down mode.
C.3
Input Signal Transitions—Reducing Overshoots and
Undershoots When Using Buffers or Transceivers
As faster, high-drive devices such as transceivers or buffers drive input signals to flash memory
devices, overshoots and undershoots can sometimes cause input signals to exceed flash memory
specifications. (See “DC Voltage Characteristics” on page 20.) Many buffer/transceiver vendors
now carry bus-interface devices with internal output-damping resistors or reduced-drive outputs.
Internal output-damping resistors diminish the nominal output drive currents, while still leaving
sufficient drive capability for most applications. These internal output-damping resistors help
reduce unnecessary overshoots and undershoots. Transceivers or buffers with balanced- or light-
drive outputs also reduce overshoots and undershoots by diminishing output-drive currents. When
considering a buffer/transceiver interface design to flash, devices with internal output-damping
resistors or reduced-drive outputs should be used to minimize overshoots and undershoots. For
additional information, please refer to AP-647,
5 Volt Intel StrataFlash
Memory Design Guide
(Order Number: 292205).
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| PC28F256J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F128J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F640J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F320J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F128J3C-120 | Intel StrataFlash Memory (J3) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F640J3C-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F640J3C-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F640J3D75 | 制造商:Intel 功能描述: |
| PC28F640J3D-75 | 制造商:Intel 功能描述:NOR Flash, 4M x 16, 64 Pin, Plastic, BGA |
| PC28F640J3D75A | 功能描述:IC FLASH 64MBIT 75NS 64EZBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
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