- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369948 > PC28F640J3C-120 (Intel Corp.) Intel StrataFlash Memory (J3) PDF資料下載
參數(shù)資料
| 型號： | PC28F640J3C-120 |
| 廠商： | Intel Corp. |
| 英文描述： | Intel StrataFlash Memory (J3) |
| 中文描述： | 英特爾StrataFlash存儲器（J3） |
| 文件頁數(shù)： | 34/72頁 |
| 文件大小： | 905K |
| 代理商： | PC28F640J3C-120 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁
256-Mbit J3 (x8/x16)
34
Datasheet
9.1.4
Standby
CE0, CE1, and CE2 can disable the device (see
Table 13 on page 33
) and place it in standby mode.
This manipulation of CEx substantially reduces device power consumption. D[15:0] outputs are
placed in a high-impedance state independent of OE#. If deselected during block erase, program, or
lock-bit configuration, the WSM continues functioning, and consuming active power until the
operation completes.
9.1.5
Reset/Power-Down
RP# at V
IL
initiates the reset/power-down mode.
In read modes, RP#-low deselects the memory, places output drivers in a high-impedance state, and
turns off numerous internal circuits. RP# must be held low for a minimum of t
PLPH
. Time t
PHQV
is
required after return from reset mode until initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The CUI is reset to read array mode and Status Register is
set to 0x80.
During block erase, program, or lock-bit configuration modes, RP#-low will abort the operation. In
default mode, STS transitions low and remains low for a maximum time of t
PLPH
+ t
PHRH
until the
reset operation is complete. Memory contents being altered are no longer valid; the data may be
partially corrupted after a program or partially altered after an erase or lock-bit configuration. Time
t
PHWL
is required after RP# goes to logic-high (V
IH
) before another command can be written.
As with any automated device, it is important to assert RP# during system reset. When the system
comes out of reset, it expects to read from the flash memory. Automated flash memories provide
status information when accessed during block erase, program, or lock-bit configuration modes. If
a CPU reset occurs with no flash memory reset, proper initialization may not occur because the
flash memory may be providing status information instead of array data. Intel StrataFlash
memory family devices allow proper initialization following a system reset through the use of the
RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system
CPU.
相關PDF資料 |
PDF描述 |
|---|---|
| PC28F256J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F128J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F640J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F320J3C-115 | Intel StrataFlash Memory (J3) |
| PC28F128J3C-120 | Intel StrataFlash Memory (J3) |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PC28F640J3C-125 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F640J3C-150 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel StrataFlash Memory (J3) |
| PC28F640J3D75 | 制造商:Intel 功能描述: |
| PC28F640J3D-75 | 制造商:Intel 功能描述:NOR Flash, 4M x 16, 64 Pin, Plastic, BGA |
| PC28F640J3D75A | 功能描述:IC FLASH 64MBIT 75NS 64EZBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:StrataFlash™ 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標準包裝:136 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步，DDR II 存儲容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應商設備封裝:165-CABGA（13x15） 包裝:托盤 其它名稱:71P71804S200BQ |
發(fā)布緊急采購，3分鐘左右您將得到回復。