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參數(shù)資料
| 型號(hào)： | P95020ZNQGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 電源管理 |
| 英文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132 |
| 封裝： | QFN-132 |
| 文件頁(yè)數(shù)： | 98/137頁(yè) |
| 文件大?。?/td> | 3533K |
| 代理商： | P95020ZNQGI8 |
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P95020 / Preliminary Datasheet
Revision 0.7.10
63
2010 Integrated Device Technology, Inc.
STJITTER
Short Term Jitter (peak-to-peak)
24, 48 MHz Output
200
ps
32 kHz Output
300
ns
tPU
Power-up Time
From minimum VDD_CKGEN18 and
VDD_CKGEN33 to outputs stable to
±1% Note 2
3
ms
From stable crystal 32kHz input to
stable output
300
ms
Notes:
1.
Measured with a 5pF load.
2.
Power-up time for TCXO derived output frequencies only after TCXO has stabilized.
4.3
CKGEN - PLL CONTROL
The PLL in the CKGEN module is powered on/off by setting bits [2:0] in the CKGEN_PLL_CFG register as shown below.
S2
S1
S0
PLL behavior
0
PLL OFF
0
1
PLL power up with 26MHz TCXO_IN as
reference clock
0
1
0
PLL power up with 32kHz XTAL_IN as
reference clock
0
1
PLL power up with 26MHz TCXO_IN
as reference clock
1
0
PLL OFF
1
0
1
PLL power up with 12MHz TCXO_IN as
reference clock
1
0
PLL power up with 13MHz TCXO_IN as
reference clock
1
PLL power up with 19.2MHz TCXO_IN
as reference clock
The 12 MHz and 48 MHz outputs are enabled/disabled by setting bits [7:6] in the CKGEN_PLL_CFG register. One or
both of the clock outputs will be enabled when a “1” is written into the corresponding register location for the output in
question.
4.4
CKGEN
– OSCILLATOR CIRCUIT
The CKGEN module may use an external 32.768 kHz crystal connected to the XTALIN pin. The oscillator circuit does not
require any external resistors or capacitors to operate. Table 15 specifies several crystal parameters for the external
crystal. The typical startup time is less than one second when using a crystal with the specified characteristics.
Table 15 - Crystal Specifications
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
COMMENTS
fo
Nominal Frequency
32.768
kHz
ESR
Series Resistance
80
k
CL
Load Capacitance
12
pF
4.5
CKGEN - CKGEN POWER SOURCE
The CKGEN module receives its power from an on-chip LDO. The CKGEN power is controlled
via the “PSTATE_ON” bit
in the Power State and Switch Control Register (see section 13.3.10). Setting that register is automatic whenever there is
an interrupt targeting the embedded processor pending. The
“PSTATE_ON” bit can be cleared by writing a logic “1” if
software wants to power down the CKGEN. Please be aware that powering down the CKGEN should be the last
operation by the software, since once CKGEN is powered down, there will be no clock for the internal register access bus
and IC. The P95020 has a minor delay when the PSTATE_ON bit is cleared to allow the
“cleaning” access to be
finished.
When CKGEN is powered, the 8M clock will be available so the IC/processor will be active. The chip
s registers can be
accessed. However, the PLLs will still not be on. To turn on the PLLs, S2:S0 registers need to be set.
4.6
CKGEN
– CLOCK ACCURACY
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match between the
capacitive load of the oscillator circuit and the capacitive load for which the crystal was trimmed. Additional error is added
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