
P95020 / Preliminary Datasheet
Revision 0.7.10
133
2010 Integrated Device Technology, Inc.
18.0 APPLICATIONS INFORMATION
18.1 EXTERNAL COMPONENTS
The P95020 requires a minimum number of external components for proper operation.
18.2 DIGITAL LOGIC DECOUPLING CAPACITORS
As with any high-performance mixed-signal IC, the P95020 must be isolated from the system power supply noise to
perform optimally. A decoupling capacitor of 0.01
μF must be connected between each power supply and the PCB
ground plane as close to these pins as possible. For optimum device performance, the decoupling capacitor should be
mounted on the component side of the PCB. Avoid the use of vias in the decoupling circuit.
18.3 CLASS_D CONSIDERATIONS
The CLASS_D amplifier should have one 330uF and one 0.1uF capacitor to ground at its VDD pin.
The CLASS_D output also should have a series connected snubber consisting of a 5.1 ohm, 0603 resistor and a 220pF
capacitor across the speaker output pins. No other filtering is required.
The CLASS_D BTL plus and minus output traces must be routed side by side in pairs.
18.4 SERIES TERMINATION RESISTORS
Clock output traces over one inch should use series termi
nation. To series terminate a 50Ω trace (a commonly used trace
impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal
impedance of the clock output is 20Ω.
18.5 IC EXTERNAL RESISTOR CONNECTION
The SCK and SDATA pins can be connected to any voltage between 1.71 V and 3.6 V.
18.6 CRYSTAL LOAD CAPACITORS
To save discrete component cost, the P95020 integrates on-chip capacitance to support a crystal with CL=10 pF. It is
important to keep stray capacitance to a minimum by using very short PCB traces between the crystal and device. Avoid
the use of vias if possible.
18.7 PCB LAYOUT CONSIDERATIONS
For optimum device performance and lowest output phase noise, the following guidelines should be observed.
1.
The 0.01μF decoupling capacitors should be mounted on the component side of the board as close to the VDD pin as
possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to each VDD pin
should be kept as short as possible, as should the PCB trace to the ground via.
2.
The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead they should be separated and away from other traces.
3.
To minimize EMI, the 33Ω series termination resistor (if needed) should be placed close to the clock output.
4.
An optimum layout is one with all components on the same side of the board, minimizing vias through other signal
layers. Other signal traces should be routed away from the P95020. This includes signal traces just underneath the
device, or on layers adjacent to the ground plane layer used by the device.
18.8 POWER DISSIPATION AND THERMAL REQUIREMENTS
The power dissipated in the P95020 will depend primarily
on the total internal power dissipation and the junction
temperature. Careful consideration must be given to the
overall thermal design. Actual thermal resistance
JA
must be determined at the customers end product level,
being based on the end package design parameters and
available device internal cooling. See
Figure 37 for
required package power de-rating.
18.9 TYPICAL BLOCK PERFORMANCE
CHARACTERISTICS GRAPHS
This section is TBD.
110
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120
-40
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90 100 110 120 130
-30 -20 -10
0
R
at
ed
P
ow
er
(%
)
Junction Temperature (°C)
Figure 37 – Power Derating Curve (Typical)