參數(shù)資料
型號： P95020ZNQGI8
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 電源管理
英文描述： 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC132
封裝： QFN-132
文件頁數(shù)： 113/137頁
文件大?。?/td> 3533K
代理商： P95020ZNQGI8
P95020 / Preliminary Datasheet
Revision 0.7.10
77
2010 Integrated Device Technology, Inc.
SYMBOL
DESCRIPTION
CONDITIONS
MIN
TYP
MAX
UNIT
(BUCK1000)
ICLP
Full Scale Cycle by Cycle Current Limit
(BUCK500)
Full Scale Cycle by Cycle Current Limit
(BUCK1000)
0xA081 [3:2], 0xA083 [3:2],
0xA085 [3:2] both bits set to 1
650
1200
1050
1800
mAPK
I
CLP
Cycle by Cycle Current Limit Step Size
4 preset levels
25
%
ISCP
Switch Peak Short Circuit Current (BUCK500)
Switch Peak Short Circuit Current (BUCK1000)
ISCP is a secondary current
protection to prevent over current
runaway.
1.3
2.25
APK
RDS-ON-HS
High Side Switch On Resistance (BUCK500)
High Side Switch On Resistance (BUCK1000)
ISW = -50mA
0.5
0.25
RDS-ON-LS
Low Side Switch On Resistance (BUCK500)
Low Side Switch On Resistance (BUCK1000)
ISW = 50mA
0.5
0.25
fPWML
PWM Mode Clock Frequency (Low)
Note 1, Note 4, Note 6
1
MHz
fPWMH
PWM Mode Clock Frequency (High)
Note 1, Note 4, Note 6
2
MHz
DMAX
PWM Mode Max Duty Cycle
100
%
tON(MIN)
Minimum Output On Time
75
ns
tSFTSLEW
Soft Start Output Slew Rate
12.5
mV/s
IQS
IQPFM
IQPWM
Quiescent Operating Current
Not operating
– Shutdown Mode
Operating (No Load) PFM Mode
Operating (No Load) PWM Mode
Note 1, Note 5
1
60
3.5
A
mA
ILEAKSW
Leakage Current Into SW pin,
Shutdown Mode, VSW=4.5V,
DCDC_GLOBAL_EN (0x05)=0;
1
A
ILEAKVIN
Leakage Current Into VIN pin
Shutdown Mode, VIN = 4.5V,
VSW=0V
DCDC_GLOBAL_EN (0x05) = 0;
1
A
IFDBK
Input Current Into FDBK pins
Operation Mode
-1
+1
A
ZFDBK_OFF
FDBK Pull Down Resistance in Shutdown
Shutdown Mode
7.1
k
UVLO
Under Voltage Lock Out Threshold
VSYS Rising
2.85
2.95
V
UVLOHYST
Under Voltage Lock Out Hysteresis
150
mV
Notes:
1.
Guaranteed by design and/or characterization.
2.
Maximum output voltage limited to (VIN - IPEAK x RDS-ON_P).
3.
Component value is COUT =22 F, L=4.7H, CIN=10F.
4.
Buck clock will be coming from external crystal through PLL. The resultant frequency will be in 1% range from the
nominal.
5.
BUCK1000, BUCK500 control register addresses / bits.
Description
Address (I2C)
Value
Not Operating
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
0x05 [0:0] = 0
0x05 [1:1] = 0
0x05 [2:2] = 0
Operating (No Load) PFM Mode
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
0x80 [0:0] = 1
0x82 [0:0] = 1
0x84 [0:0] = 1
Operating (No Load) PWM
Mode
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
0x80 [0:0] = 0
0x82 [0:0] = 0
0x84 [0:0] = 0
6.
Buck regulator clock frequency control register addresses.
Description
Address (I2C)
Value
1 MHz
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
0x80 [1:1] = 0
0x82 [1:1] = 0
0x84 [1:1] = 0
2 MHz
Buck#0 (500mA)
Buck#1 (500mA)
Buck#2 (1000mA)
0x80 [1:1] = 1
0x82 [1:1] = 1
0x84 [1:1] = 1
8.3
BUCK CONVERTERS
– TYPICAL PERFORMANCE CHARACTERISTICS
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